Differential Pair Impedance Calculator
Estimate differential impedance from trace width, spacing, copper thickness, and stackup—or find a starting trace width for your target impedance.
Use this closed-form estimate to explore geometry. Confirm production dimensions with your PCB fabricator’s stackup model and impedance verification process.
Calculate your differential pair
Enter finished copper dimensions. Spacing S is the gap between the two trace edges, not their center-to-center pitch.
Calculated estimate
Select your geometry and calculate to see the result.
- Trace width W
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- Odd-mode Zodd, per trace
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- Isolated-trace Z0
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Zodd = Zdiff / 2 for this symmetric pair. Isolated-trace Z0 is the same trace without its coupled neighbor; it is not the per-trace odd-mode impedance.
How sensitive is this geometry?
One input changes at a time; all others stay at the calculated baseline. These are exploration steps, not manufacturing tolerance limits or a combined worst case.
| Input change | Lower input | Higher input |
|---|
A geometry estimate—not a channel sign-off
This tool does not model soldermask, etch shape, multiple dielectrics, frequency-dependent losses, vias, connectors, or skew. A result inside your selected band does not establish interface compliance or production yield.
Three details that change the answer
Edge gap, not pitch
Enter the empty distance between the two traces as S. For equal widths, center-to-center pitch is W + S; the overall pair span is 2W + S. Do not enter either of these as the gap.
H depends on the structure
For microstrip, H is the dielectric between the trace bottom and its plane. For this symmetric stripline model, H is the equal dielectric clearance on each side of the copper. Inner plane-to-plane distance is B = 2H + T.
Use finished geometry
Ask for the fabricated width, gap, copper thickness, dielectric build, and Dk convention. CAD width and starting foil weight may not describe the finished conductor cross-section.
Equations & screening limits
The calculator uses the closed-form expressions shown in Figure 9-4 of TI’s SN65MLVD203B datasheet, Rev. B. All lengths use the same units; ln is the natural logarithm. Output impedance is in ohms.
Edge-coupled microstrip
Equal surface traces, one reference plane, and air above the dielectric.
Z0 = 87 / √(εr + 1.41) × ln[5.98H / (0.8W + T)]
Zdiff = 2Z0 × [1 − 0.48 × exp(−0.96S/H)]Symmetric edge-coupled stripline
Equal traces centered between two planes, with the same dielectric above and below.
Z0 = 60 / √εr × ln[1.9(2H + T) / (0.8W + T)]
Zdiff = 2Z0 × [1 − 0.347 × exp(−2.9S/H)]What the width solver holds fixed
The solver changes W only. Edge gap S, height H, thickness T, dielectric constant, and topology remain fixed. It solves the same equation algebraically, then recalculates Zdiff before displaying the result.
Center-to-center pitch changes when W changes. If your layout fixes pitch instead of edge gap, this is not the correct constraint.
When the calculator stops
Accepted dimensions: W and S 0.005–10 mm, H 0.025–2 mm, and T 1–200 µm. Ratios must also satisfy W/H 0.1–2, S/H 0.2–5, and T/H ≤ 0.25; εr must be 2–10.
These are intentionally limited software guardrails, not a guarantee of equation accuracy. No result is extrapolated beyond them. The width solver reports the reachable target range when it cannot return a width inside this window.
What to check next
Impedance is one part of the interconnect. Match the next checks to the device, interface generation, and board construction.
Confirm the build
- Signal layer and adjacent reference planes.
- Finished W, S, T, dielectric thickness, and material data.
- Soldermask, etch profile, and fabrication limits.
- Approved impedance target and acceptance method.
Check the entire route
- Pair symmetry, uniform geometry, and allowed skew.
- Continuous return paths across layer transitions.
- Via stubs, breakout geometry, pads, and connectors.
- Separation from other pairs and noise sources.
Agree verification
- Fabricator’s modeled dimensions and allowed tolerances.
- Impedance coupon, TDR method, and reporting scope.
- Channel loss, timing, and eye requirements when applicable.
- Engineering approval before fabrication release.
Differential impedance questions
Is a 100 Ω differential pair two 50 Ω traces?
Each trace has 50 Ω odd-mode impedance in a symmetric 100 Ω pair. That is not necessarily the isolated single-ended impedance of either trace. Coupling between the traces changes the odd-mode result.
Should I change width or spacing first?
Start with the stackup and fabrication constraints. In this model, increasing W lowers Zdiff, while increasing S raises it toward the uncoupled limit. Use the width solver only when S can remain fixed, then review the resulting width and pitch against your layout rules.
Why is there no frequency input?
This is a quasi-static closed-form estimate, not a frequency-dependent channel model. Use an appropriate stackup Dk, then evaluate conductor and dielectric loss, dispersion, and interconnect discontinuities in a suitable solver for your signal bandwidth.
Does the microstrip result include soldermask?
No. It assumes air above the traces. If your pair is covered by soldermask, embedded in dielectric, or close to coplanar ground copper, use the matching coated, embedded, or coplanar model. There is no universal percentage correction applied here.
Can I use the total distance between stripline planes as H?
No. For this calculator, both trace-to-plane dielectric clearances equal H, excluding the trace thickness. If the inner plane-to-plane distance is B, enter H = (B − T) / 2, using the same units for B and T. This only applies to a centered trace layer.
Does “inside the selected band” mean the board will pass?
No. It only compares this calculation with your chosen target and percentage band. It does not include combined manufacturing variation, material variation, measurement uncertainty, or the rest of the channel. Agree the production model and verification requirements with your fabricator.
Continue your PCB checks
Need the components for your design?
Send the approved part numbers or BOM, quantities, package requirements, and delivery schedule. YURUNOX can review sourcing options for your interface ICs, connectors, protection devices, and supporting components.
Technical references
- Texas Instruments — SN65MLVD203B, Rev. B, Figure 9-4: closed-form impedance equations.
- Polar Instruments — AP161: differential geometry and finished dimensions.
- Analog Devices — Introduction to Common Printed Circuit Transmission Lines.
- Polar Instruments — transmission-line field solver and frequency-dependent models.
- Texas Instruments — High-Speed Interface Layout Guidelines.