Flyback Transformer Inductance Sizer
Find a starting primary magnetizing inductance, then check peak current, demagnetization time, winding RMS current, and voltage stress across the input range.
For a single-output, single-switch, diode-rectified flyback using a fixed-frequency DCM model. This is not a CCM, quasi-resonant, active-clamp, or isolation-certification tool.
Start with the power and timing limits
Use the DC bus range at the primary—not AC RMS mains voltage. Lm is the primary magnetizing inductance with the other windings open, not leakage inductance.
Inductance & operating result
Calculate to review the design window.
Nominal inductance window
Current & timing envelope
All 8 input / Lm / frequency corners
| VIN / Lm / f | On / off | Reserve | IPRI,pk | Mode |
|---|
Core & turns screen
Equivalent gap ignores finite core reluctance and fringing. It is not a machining dimension. Verify AL, inductance under bias, losses, temperature, winding fit, and insulation with the magnetics supplier.
Semiconductor voltage screen
Voltage estimates omit bus transients, output overshoot, layout parasitics, and unspecified ringing. No avalanche or repetitive-stress approval is implied.
An inductance is not a finished transformer
Controller dynamics, startup, faults, leakage, AC copper loss, core loss, winding temperature, insulation, creepage, and clearance require separate design and verification. Offline supplies involve hazardous voltages; these results do not establish electrical safety.
Separate energy, timing, and magnetics
Start from a zero-current ramp
Ecycle = Pbudget / f
IPK = √(2 × Pbudget / (Lm × f))
η is entered as a fraction in the equations. Assigning POUT/η to magnetizing energy is an initial design allowance. Losses are not distributed among the windings, switch, rectifier, or core.
Leave room after demagnetization
DON = Lm × IPK × f / VIN
DOFF = Lm × IPK × f / VR
Didle = 1 − DON − DOFF
A positive Didle indicates DCM in this idealized model; zero is the boundary. A negative result invalidates the zero-start-current assumption. It is not a CCM solution.
Use peak and RMS separately
ISEC,pk = (NP / NS) × IPK
ISEC,rms = ISEC,pk × √(DOFF / 3)
RMS estimates are for the full switching period. They are energy-budget estimates, not a loss-resolved current prediction. The primary peak does not change with VIN in this fixed-power, fixed-Lm, fixed-f DCM model.
The timing ceiling includes tolerance
Lreset = [(1 − Didle,required) / (1/VIN,min + 1/VR)]² / (2 × Pbudget × fmax)
Lnom,max = min(Lduty, Lreset) / (1 + tL)
Lnom,min = 2 × Pbudget / [fmin × Ilimit² × (1 − tL)]
The lower bound is included only when a peak-current ceiling is entered. If the bounds overlap, sizing starts at 90% of the timing ceiling, raised to the current-derived lower bound if necessary. This is a continuous target, not a catalog-value selection.
Flux swing and the gap are separate checks
NP,min = ceil(max(Lm × IPK) / (Ae × ΔBallow))
AL,target = Lm,nom / NP²
gequivalent ≈ µ0 × NP² × Ae / Lm,nom
Use Ae in m² and Lm in H. The flux screen covers the required operating swing only; residual flux and fault-current peaks can raise absolute B. The gap expression assumes gap-dominated reluctance, without fringing.
What to change when a check fails
| Finding | Review next | Trade-off to retain |
|---|---|---|
| Too little reset reserve | Reduce Lm, increase reflected voltage, reduce power, or revisit frequency. | Lower Lm raises peak current. Higher reflected voltage increases MOSFET flat-top stress. |
| Peak current too high | Increase Lm within the timing window, or revisit power, frequency, and controller capability. | Higher Lm consumes more of the switching period. No overlap between limits means no feasible DCM value under these assumptions. |
| Flux excursion too high | Increase primary turns or core area and rework the gap and winding arrangement. | Keep the actual turns ratio consistent. More turns affect copper length, fill, leakage, and capacitance. |
| Flat-top voltage near the device limit | Review turns ratio, the clamping network, real ringing, bus extremes, and derating. | Reducing NP/NS lowers MOSFET reflected stress but raises rectifier reverse stress. |
Define the winding specification
Electrical identity
Provide the controller, input bus range, output, frequency range, primary-referred Lm and tolerance, turns and polarity, peak/RMS currents, and leakage target. Include how and where inductance is measured.
Magnetic and thermal limits
Agree the material, usable flux range, bias-dependent inductance, winding resistance, AC loss, and temperature rise. A small-signal AL measurement alone does not verify operation at peak current.
Construction and isolation
Specify the package, pinout, winding stack, insulation system, working voltage, and required qualification. Select creepage, clearance, and test conditions through the applicable product-safety design process.
Flyback inductance questions
Does this tool calculate CCM or quasi-resonant operation?
No. It assumes each primary-current ramp starts at zero at the entered frequency. CCM needs a nonzero valley-current model. Quasi-resonant and boundary controllers vary timing and may have frequency clamps; use their device-specific design method.
Which tolerance corner is most restrictive?
Higher Lm and frequency consume more cycle time. Lower Lm and frequency increase peak current. The flux excursion increases with higher Lm and lower frequency. The sizer evaluates both input endpoints and all four Lm/frequency combinations.
Why is the energy-budget secondary current not my load current?
The tool applies POUT/η to the energy packet while using ideal winding-current shapes. It does not assign each loss to a physical element. Treat the RMS and peak values as first-pass sizing estimates, then use a loss-resolved model and measurements for final ratings.
Can the equivalent gap be used as a spacer thickness?
Not directly. Finite core permeability, gap distribution, geometry, and fringing change the required physical gap. Use the target AL and operating inductance with the core manufacturer's or transformer supplier's design process.
What if the calculated secondary turns are fractional?
Choose a realizable integer winding pair, update NP/NS, and calculate again. The tool does not round secondary turns silently because that changes reflected voltage, timing, and device stress.
Does meeting the flux-swing limit prove no saturation?
No. ΔB describes the operating excursion, not absolute peak flux. Check residual flux, material temperature, inductance roll-off, startup, current-limit tolerances, and propagation-delay overshoot separately.
Continue the power-stage review
Source the parts behind your design
Send the controller, MOSFET, rectifier, magnetics part number or specification, quantity, and required date for an order-specific review.
Technical references
- Texas Instruments — Designing a DCM flyback converter. DCM timing and reflected-voltage design.
- Analog Devices — Designing Flyback Converters Using Peak-Current-Mode Controllers. Mode-specific design, winding currents, and semiconductor stress.
- Analog Devices — MAXREFDES1176. An example of magnetizing-energy and transformer-specification calculations; not a preset for this tool.
- Texas Instruments — Inductor and Flyback Transformer Design. Core loss, saturation, inductance factor, gaps, and fringing.