High-Voltage Digital Isolator Delay Tool
Build a worst-case timing budget across an isolation barrier. Check edge delay, pulse-width distortion, parallel-channel alignment, round-trip response, and the remaining sampling margin.
A delay calculation cannot verify working voltage, isolation class, creepage, clearance, CMTI, surge, safety certificates, layout, or system compliance.
Check a one-way or round-trip timing path
Enter guaranteed limits for the exact orderable device, supply, load, and temperature conditions. Defaults are illustrative and do not describe a particular isolator.
Isolation-path timing results
Enter guaranteed timing limits to calculate.
Calculated timing details
Do not infer high-voltage safety from timing
Propagation delay, data rate, PWD, and CMTI describe different behaviors. Check the exact device’s working voltage, temporary withstand and surge ratings, insulation class, package geometry, certification scope, pollution degree, altitude, PCB spacing, and applicable equipment standard.
Four limits answer different questions
tPLH and tPHL locate output edges
tPLH is the low-to-high propagation delay and tPHL is the high-to-low propagation delay. Their minimum and maximum limits locate the earliest and latest corresponding output edges. Supply voltage, temperature, output loading, and logic conditions can change the specification.
PWD changes high and low pulse widths
For a non-inverting channel, output high width equals input high width plus tPHL minus tPLH. Output low width changes by the opposite amount. TI specifies pulse-width distortion as |tPHL − tPLH| in its ISO723x datasheet.
Channel skew is not part-to-part skew
Channel-to-channel output skew compares specified outputs of one device under matched conditions. Part-to-part skew compares terminals on separate devices under matched conditions. Use the definition that matches the physical paths; do not substitute the smaller number automatically.
Round-trip delay can limit a fast interface
A one-way data-rate rating does not prove that returned data arrives before a controller’s sampling edge. An SPI clock can cross the barrier, trigger a peripheral response, and send data back through a second channel. TI’s isolated SPI timing brief highlights this round-trip limit.
Equations and conservative assumptions
All delay inputs are in nanoseconds. Frequency is in megahertz, so the signal period in nanoseconds is 1000 divided by frequency.
Pulse-width range
Δmin = max(tPHL,min − tPLH,max, −PWDmax)
Δmax = min(tPHL,max − tPLH,min, +PWDmax)
Highout = Highin + N × Δ
Lowout = Lowin − N × Δ
For cascaded stages, the tool stacks worst-case distortion linearly. It assumes non-inverting logic behavior at the path level; an inverting device changes the label of high and low but still needs edge-specific review.
Propagation and skew
Fall path = N × tPHL + other delay
Alignment bound = N × selected skew + path mismatch
The “other delay” terms are added to the isolator delay. Alignment is an upper-bound sum, not a statistical RSS result. Correlation, jitter, board mismatch, receiver thresholds, and rise/fall time require separate evidence.
Round-trip sampling
Required window = Loopmax + receiver setup + allowance
Available window = period × sampling-window fraction
Margin = available − required
The calculated loop ceiling is the frequency at which the entered available-window fraction just equals the required window. Verify the actual sampling edge, clock phase, protocol behavior, and endpoint timing.
Pulse and data-rate ceilings
Lowin = period × (1 − duty)
Output pulse margin = min(Highout,min, Lowout,min) − receiver minimum
Alternating-pattern demand = 2 × frequency Mb/s
The final displayed ceiling is the lowest of the applicable pulse, data-rate, and round-trip ceilings. This arithmetic result is not a recommended operating frequency and does not replace datasheet or system validation.
Build a complete isolated-interface review
Map every channel direction
Document input and output domains, logic levels, default states, enables, startup behavior, inversion, pulse polarity, and whether the interface needs a return path.
Match timing conditions
Use limits for the actual supplies, output load, temperature, channel combination, data pattern, and package. Add controller, peripheral, transceiver, cable, and PCB timing once.
Review the insulation system
Define working voltage and transients, basic or reinforced insulation, certification needs, environment, spacing, and lifetime. Then compare current certificates for the complete orderable number.
Digital-isolator timing questions
Why can an isolated SPI link fail below the isolator’s data-rate rating?
The controller may need returned data within part of one clock period. Two isolator crossings, peripheral clock-to-output, setup time, traces, buffers, and uncertainty can consume that window even when every one-way channel meets its data-rate limit.
Is maximum propagation delay enough for PWM?
No. Absolute delay moves both edges, while the difference between tPLH and tPHL changes pulse width and duty cycle. Check PWD, minimum pulse width, switching frequency, output edge rates, load, and the receiving circuit’s threshold behavior.
Can I add channel skew and PWD together?
They answer different path questions and may already share underlying delay variation. This tool uses PWD for one signal’s high/low pulse and skew for the relative alignment of parallel paths. Build a specific timing diagram before combining terms so the same variation is not counted twice.
Does CMTI belong in the nanosecond delay budget?
Not as another propagation-delay term. CMTI describes behavior during a common-mode voltage transient under specified test conditions. A transient can cause errors if system dv/dt exceeds the guaranteed capability, but simply adding a CMTI number to delay has no physical meaning.
Does a “5 kV” rating prove suitability for mains?
No. A temporary dielectric withstand value is not the same as continuous working voltage or a complete insulation design. Check basic or reinforced classification, working and surge ratings, certificates, creepage, clearance, PCB layout, environment, and the relevant end-equipment requirements.
Can I use typical delay values for the final budget?
Typical values help estimate nominal behavior but are not guaranteed limits. Use specified maximum and minimum values across the required conditions, plus justified external timing terms and design allowance. Confirm the latest documentation for the exact part and suffix.
Continue the isolation review
Need a digital isolator for a defined interface?
Send the part number or channel map, direction, logic supplies, timing limits, isolation requirements, package, quantity, and required date. YURUNOX can review the sourcing requirement and available supply options.
Technical references
- Texas Instruments — ISO723x digital isolator datasheet: propagation delay, PWD, channel skew, and part-to-part skew definitions.
- Texas Instruments — Digital Isolators for Serial Interfaces, SLLA522: round-trip clock and data timing.
- Analog Devices — ADuM228x product documentation: an example of separately specified propagation delay, PWD, and channel matching.