LDO Regulator Resistor Divider Sizer
Select a feedback resistor for your target output voltage. Compare E24 or E96 values, include reference and resistor tolerances, and check how feedback-pin current changes the result.
For a positive adjustable LDO whose FB pin is regulated to a ground-referenced voltage. Confirm the exact device equation, output range, capacitor requirements, and operating limits.
Size or check the feedback divider
RTOP connects OUT to FB. RBOTTOM connects FB to ground. The bottom resistor stays at your entered value; sizing selects the top resistor only.
Divider result
Calculate to review the divider.
Target & error budget
Compare nearby top values
| RTOP | Nominal VOUT | Output range | Budget |
|---|
Divider currents & resistor dissipation
These are regulated-state estimates. Resistor wattage, working voltage, self-heating, leakage, and device-specific resistance limits still need checking.
Operating-condition screen
DC accuracy is not loop stability
This model does not choose CIN, COUT, ESR, or feed-forward capacitance. It does not predict PSRR, noise, startup, transient response, or temperature rise. A valid divider ratio cannot establish that the LDO will regulate under every operating condition.
Confirm what the FB pin regulates
The equation below applies when the regulator holds FB at VREF relative to ground. Resistor names in a manufacturer datasheet may be reversed; match the physical connections.
Include the bias-current term
ITOP = IBOTTOM + IFB
VOUT = VREF × (1 + RTOP / RBOTTOM) + IFB × RTOP
RTOP,ideal = (VTARGET − VREF) / (VREF / RBOTTOM + IFB,nom)
Current flowing into FB raises the modeled output relative to the zero-bias equation. Current flowing out lowers it. The voltage effect grows with the top resistance.
- Use the signed current direction, not only its magnitude.
- The selected network must keep ITOP positive across the entered bounds.
- This is not an LM317-style output-to-ADJ reference model, a negative LDO, or a current-source SET-pin regulator.
From nominal ratio to a DC envelope
Hold the bottom resistor fixed
The tool searches top values from 100 Ω to 10 MΩ in E24 or E96. Among candidates inside the output budget, it chooses the smallest absolute nominal voltage error. If none qualify, the closest value is displayed for review only.
Evaluate all 16 corners
Two reference limits, two top-resistor limits, two bottom-resistor limits, and two FB-current limits form 16 endpoint combinations. The displayed minimum and maximum are deterministic bounds, not a statistical confidence interval.
Check more than the ratio
Verify the actual input and adjustable-output ranges, UVLO, dropout under load, total OUT-pin current, minimum load, and allowable dissipation. Blank optional limits are not a pass.
Dropout and output current
IOUT,max = ILOAD,max + ITOP,max
Divider-only preload = ITOP,min
The dropout screen uses the highest modeled output. The preload check assumes no external load. Positive headroom alone does not verify the LDO input range, enable threshold, bias supply, or stability.
A conservative IC power screen
+ VIN,max × (IGND,max + |IFB|max)
This combines independent worst-case terms and an absolute FB-current allowance, so it is a conservative bound within the regulated DC model—not an exact thermal prediction. Power is withheld if an entered dropout or current condition fails.
The allowable power input must already reflect board cooling, ambient temperature, and design margin. External divider-resistor heat is reported separately.
Balance accuracy, current, and stability
Do not scale the pair blindly
The same resistor ratio can produce different bias-current error, noise, leakage sensitivity, and divider consumption. Stay within the device's resistance guidance and check the whole error budget when increasing resistance.
Keep error sources separate
Nominal rounding, reference accuracy, resistor variation, and FB current are included here. Line/load regulation, board leakage, wiring drops, and temperature effects are excluded unless you deliberately include them in an applicable input bound.
Follow the capacitor guidance
Use the exact LDO's requirements for effective capacitance, ESR, layout, and feed-forward compensation. Account for ceramic-capacitor DC bias. A DC divider result does not determine whether the control loop is stable.
LDO divider questions
Which resistor is the top resistor?
The top resistor connects the regulated output to the FB junction. The bottom resistor connects FB to ground. Use the connections rather than R1/R2 names, because manufacturers do not all use the same numbering.
Does E96 automatically mean 1% accuracy?
No. E96 defines nominal preferred values. Actual component tolerance is specified by the selected resistor and ordering code. The calculator uses your separate top and bottom tolerance inputs.
Why does my LDO datasheet subtract the bias term?
Its adjust current may be defined as flowing out of the pin. This tool defines positive current into FB, so enter an outward current as negative. The resulting plus-signed term then subtracts the voltage contribution automatically.
Can I use this for an LM317 or a single SET resistor?
No. An LM317 regulates a reference between OUT and ADJ, while some LDOs program output with a SET-pin current and one resistor. Their equations and loading differ from this ground-referenced two-resistor model.
Why is there no in-budget resistor?
A preferred value may miss a narrow target, or the reference, resistor, and bias-current bounds may already consume the error allowance. Use check mode for a custom pair, or review the part accuracy and resistance scale. Do not treat the closest displayed value as compliant.
Does the output range include startup and transients?
No. It is a static model for regulated operation using the supplied bounds. Startup overshoot, load steps, ripple, PSRR, instability, dropout behavior, and current limiting are outside this calculation.
Continue the power-stage review
Ready to source the regulator and resistors?
Send the exact part numbers, package, resistor values and tolerances, quantity, and required date for an order-specific sourcing review.
Technical references
- Texas Instruments — TPS735 datasheet. Adjustable feedback topology, operating modes, and capacitor guidance; not a preset for this tool.
- Analog Devices — LT3062 datasheet. An example of ADJ current flowing out of the pin and the resulting negative bias term.
- Texas Instruments — Linear Regulator Design Guide for LDOs. Dissipation, dropout, and thermal considerations.
- Vishay — Standard Ohmic Values. E-series nominal resistor values.