Microstrip Line Impedance Calculator
Estimate the impedance of an outer-layer PCB trace, or find a starting trace width for your target impedance. Include finished copper thickness and check how fabrication variations could shift the result.
Trace & substrate
Uncoated surface trace, air above, and a continuous reference plane below. Not a coplanar or differential model.
Microstrip results
Calculate to see the impedance and geometry.
Geometry & propagation
- Width / dielectric height
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- Copper / height · copper / width
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- Zero-thickness impedance, same width
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- Copper correction to impedance
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- Equivalent model width wᵣ
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- Velocity factor · delay per mm
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Use the physical width for the starting layout. The equivalent model width is a calculation term, not an additional width to add to the PCB artwork.
Fabrication variation check
—Text report includes inputs, model assumptions, and any variation checks.
Three inputs worth checking first
A plausible impedance number is only useful when the cross-section represents the board you will build.
Use the correct height
For a top-layer trace referenced to the next ground layer, enter the dielectric separation between those two copper surfaces. Do not substitute the total board thickness unless that is genuinely the trace-to-plane separation.
Use a relevant Dk
Ask for the laminate’s design permittivity appropriate to your stackup and operating conditions. A generic material name alone does not define one exact dielectric constant. The result does not automatically adjust Dk with frequency.
Allow for the real copper
Enter finished copper thickness, including plating where relevant. The model assumes a rectangular conductor. Etched sidewall taper, surface roughness, and fabricator compensation are not resolved by this calculation.
How the estimate is made
The calculator uses the Hammerstad–Jensen quasi-static model. Normalized width and copper thickness are used to estimate an equivalent wider strip, followed by the impedance and effective-permittivity corrections.
u₁ = u + Δu₁ · uᵣ = u + Δuᵣ
Z₀ = Zair(uᵣ) / √εeff,0(uᵣ)
εeff = εeff,0(uᵣ) × [Zair(u₁) / Zair(uᵣ)]²
One-way delay = length × √εeff / c
In width mode, numerical bisection finds the physical width that produces the target impedance within the permitted geometry. A target outside that interval is reported rather than forced to a boundary.
Model references: Qucs microstrip equations and the scikit-rf MLine implementation, which also clarifies the normalized-width thickness correction.
Know when to use a solver
- Supported structure: a uniform, single-ended, uncoated microstrip over one homogeneous dielectric and a continuous plane.
- Tool guardrails: εr 1–15; w/h 0.1–10; t/h ≤ 0.1; t/w ≤ 0.2; h 0.05–3.2 mm; t 0–105 µm. These are conservative software limits, not an accuracy guarantee.
- Different structures: use a suitable solver for solder mask, coplanar ground, embedded microstrip, differential pairs, multilayer dielectrics, or a nearby metal enclosure.
- Frequency behavior: dispersion, conductor and dielectric loss, roughness, radiation, bends, pads, vias, and connectors are excluded. This tool does not establish a maximum operating frequency.
Turn the result into a design decision
If the impedance is too high
For the same substrate and copper, widening the trace generally reduces its characteristic impedance. Reducing trace-to-plane separation also reduces impedance. Changing either dimension can affect routing space, coupling, stackup options, and manufacturability.
Use target-impedance mode to explore the width, then confirm the result fits the actual routing and fabrication constraints. Trace length affects the reported delay, not the uniform line’s characteristic impedance.
If production variation matters
Enable the variation check with tolerances supplied for your board. It evaluates the eight endpoint combinations of width, dielectric height, and permittivity, plus the nominal point, while keeping copper thickness fixed.
The reported envelope is a sampled sensitivity estimate, not a probability distribution, yield forecast, or guaranteed production limit. If any endpoint lies outside the tool’s limits, no complete envelope is reported. In width mode, the solved nominal width stays fixed while those variations are applied.
Prepare a controlled-impedance stackup
Share the target impedance and allowed tolerance, reference layer, laminate grade, dielectric height, finished copper, and solder-mask condition. Agree whether the fabricator may adjust the trace width and how that adjustment will be approved.
Microstrip calculator FAQ
What trace width gives 50 Ω?
There is no universal 50 Ω trace width. Select “Trace width from impedance,” enter 50 Ω, then use the dielectric height, finished copper thickness, and permittivity for your stackup. The calculated physical width is a starting point for fabrication review.
Is εeff the same as the laminate’s εr?
No. A surface microstrip’s electromagnetic field occupies both the dielectric and the air above it. Effective permittivity describes that combined propagation environment in this model; the laminate permittivity is an input material property.
Can I use this for grounded coplanar waveguide?
Not when adjacent coplanar ground materially influences the field. Ground spacing and geometry must then be included in a grounded coplanar-waveguide model. This calculator has no gap input and does not account for those side conductors.
Does the result include solder mask?
No. The model assumes air above an uncoated trace. Solder mask changes the dielectric environment, so the final coated cross-section needs a model that includes its thickness and dielectric properties.
Why does increasing copper thickness change impedance?
A finite-thickness conductor behaves differently from an infinitely thin strip. The model accounts for this through an equivalent-width correction. The displayed physical width already includes the effect of the copper thickness entered; do not add the equivalent-width correction to it again.
Is the delay valid for every operating frequency?
No. The reported delay uses quasi-static effective permittivity and route length. It excludes dispersion and discontinuities, and should not be interpreted as a broadband group-delay simulation or a measured board result.
Need components for your RF design?
Send the exact part numbers or BOM, quantities, required dates, and sourcing requirements. YURUNOX can help review electronic-component availability and order-specific supply options.