MOSFET Gate Resistor Sizer
Find an initial gate-resistor value from Miller charge, transition-time limits, and driver impedance. Compare one shared resistor with separate turn-on and turn-off paths, then review current demand and gate-drive dissipation.
For one N-channel MOSFET with a resistive voltage-source gate driver. Verify gate ringing, drain overshoot, switching loss, and pulse ratings in the actual circuit.
Size or check your gate resistors
Use Qgd for the Miller interval, not total gate charge Qg. The plateau voltage is not VGS(th), and the times below are not complete turn-on or turn-off times.
Starting-point estimates
Enter the device and driver conditions to calculate.
Resistance window
Bounds apply to the nominal external resistor, including its entered tolerance. The minimum reflects only the entered pulse-current limit; it is not a damping recommendation.
| Model quantity | Turn-on | Turn-off |
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Time & current checks
| At selected / candidate Rg | Turn-on | Turn-off |
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Gate-drive energy & dissipation
| Dissipative element | Average power | Per-edge energy |
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Average watts alone do not establish resistor suitability. Check repetitive pulse energy, peak voltage/current, ambient-temperature derating, and the resistor manufacturer’s pulse-load curves.
Keep switching and gate-drive loss separate
Qg × gate-voltage swing × frequency estimates the gate-drive energy budget. It does not calculate MOSFET drain switching loss, conduction loss, reverse recovery, or junction temperature.
Which part of switching are we estimating?
The gate path contains more than the visible external resistor. During the Miller interval, a roughly constant gate voltage lets charge-based timing provide a useful first estimate.
Bring the right datasheet values
- Qgd and plateau voltage: match the drain voltage and load current as closely as possible.
- Driver source/sink impedance: use relevant output-stage data. Do not infer a constant resistance from an absolute-maximum current alone.
- Internal Rg: include the device’s gate resistance rather than assigning the entire resistance budget to the external part.
- Total Qg: use it only for full-swing gate-drive power here—not as a substitute for Qgd.
Plateau shape and switching behavior vary with load, temperature, layout, and device construction. See Nexperia’s gate-driver fundamentals (PDF).
From gate current to resistor value
All voltages are gate-to-source referenced. The model uses one MOSFET, one effective plateau, and linear source/sink output resistances.
Miller timing
ΔVon = VHI − VM
ΔVoff = VM − VLO
Rfixed = Rdriver + Rg,internal
IM = ΔV / (Rfixed + Rexternal)
tM = Qgd / IM
Rexternal,exact = ΔV × tM / Qgd − RfixedA negative exact resistance means the requested time is faster than the model allows with zero external resistance. The calculator does not replace that result with a recommended 0 Ω part. TI gate-driver circuit fundamentals (PDF).
Tolerance & current bounds
ΔVdrive = VHI − VLO; k = tolerance / 100
Rmax,time = (ΔV × tmax / Qgd − Rfixed) / (1 + k)
Rmin,peak = max[0, (ΔVdrive / Ilimit − Rfixed) / (1 − k)]
Ipeak,worst = ΔVdrive / [Rfixed + Rexternal(1 − k)]The largest E24 value inside the interval is an initial candidate, not a ringing optimum. A shared resistor must satisfy both directions. Blank current limits leave that part of the screening incomplete; real current limiting is not simulated.
Gate-drive power
Ecycle ≈ Qg × (VHI − VLO)
Pgate ≈ Ecycle × fsw
Eedge ≈ Ecycle / 2
Pexternal,on ≈ fsw × Eedge × Ron / Rtotal,on
Pexternal,off ≈ fsw × Eedge × Roff / Rtotal,offThe power split uses an equivalent-capacitance approximation with equal energy per edge. It is a nominal estimate, not a nonlinear charge-waveform integral. For one shared resistor, add both contributions. Driver quiescent, internal switching, and supply-converter losses are excluded. TI gate-driver power-loss example (PDF).
What the model cannot decide
Parasitic inductance, Cgd variation, Miller injection, driver saturation, diode steering, parallel MOSFET sharing, and temperature shifts need circuit-specific analysis. A gate resistor also affects oscillation damping and EMC. TI external gate-resistor selection guide (PDF).
This tool does not determine a safe gate-voltage rating, dead time, drain dv/dt, avalanche margin, or resistor package. It does not model GaN gate structures or current-programmed drivers. Very fast SiC designs need their device-specific driver and layout guidance.
Supported input window
VHI: 2–30 V; VLO: −10–0 V; VM: 0.1–29.9 V and strictly between the rails; Qgd: 0.1–1,000 nC; each time limit: 1–50,000 ns; driver resistances: 0.01–100 Ω; internal Rg: 0–100 Ω; external Rg: 0–1,000 Ω; tolerance: 0–20%; optional pulse limits: 0.01–100 A; optional Qg: 0.1–5,000 nC and at least Qgd; frequency: 0.1–2,000 kHz. E24 candidates span 0.1–1,000 Ω. These are software input limits, not validated operating limits for a device.
What to verify before choosing the part
Check the complete drive path
Confirm the gate-voltage range, output-current test conditions, internal Rg, and gate-charge curve. Review the proposed resistor at both minimum and maximum drive conditions, not only nominal values.
Measure the real transition
Use appropriate probing to examine VGS and VDS. Check ringing, overshoot, unwanted turn-on, and timing at operating corners. Keep the gate loop compact and follow the driver’s return-path and decoupling guidance.
Check pulse capability
Specify resistance, tolerance, package, temperature range, and repetitive pulse requirements. A resistor with enough average wattage may still be unsuitable for short gate-current pulses.
Gate-resistor sizing questions
Why use Qgd instead of total gate charge?
Qgd describes charge associated with the drain-voltage transition in the simplified plateau model. Total Qg also covers other parts of the gate waveform. Substituting Qg for Qgd changes which interval the timing estimate describes.
Why are turn-on and turn-off values different?
The voltage across the resistive path differs: VHI − VM for turn-on and VM − VLO for turn-off. The driver may also have different source and sink impedances. Separate paths let the two transitions be adjusted independently.
What does “no candidate” mean?
The entered time and pulse-current bounds may not overlap, or no E24 value from 0.1 to 1,000 Ω lies inside their overlap. Review the driver, charge data, targets, or topology. It does not mean a negative resistor or an automatic 0 Ω link is appropriate.
Can I use VGS(th) as the plateau voltage?
No. Threshold voltage is specified at a small test current; the plateau relevant to switching load current is a different operating condition. Read a suitable gate-charge curve or use device-specific modeling and measurements.
Does the calculator size a gate-to-source pull-down?
No. It sizes the series switching resistor. A gate-to-source pull-down sets a default state and handles leakage or disconnected-driver conditions; it requires a separate analysis of leakage, bias, and switching behavior.
Can average power select the resistor wattage?
Not by itself. Review pulse-load curves, repetitive pulse energy, voltage rating, ambient derating, and the actual waveform. The equal-edge-energy estimate here is a screening aid, not a resistor qualification test.
Continue your design review
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