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PCB layout & power paths

PCB Trace Width & Current Capacity Calculator

Estimate a copper trace width for your DC load, or check the current a chosen width can carry under a legacy thermal model. Compare outer and inner layers, then review resistance, voltage drop, and power loss.

Width ↔ currentmm & milOptional voltage-drop limit
Trace width, length, and finished copper thicknessThe top view identifies trace length L and width W. A separate cross-section identifies finished copper thickness t, an outer copper trace, and an inner trace within the dielectric. Both width and thickness determine copper cross-sectional area. COPPER GEOMETRY L WDC current t Outer layerInner layer Cross-sectional area = W × t
Conceptual geometry, not to scale. Use finished copper dimensions, not the board thickness.
Start with the electrical requirement

Size a trace. Compare both layers.

Choose a calculation mode and set the allowable temperature rise. Add a voltage-drop budget when power delivery, not only heating, limits the trace.

Trace inputs
Changing units converts the existing dimensions.
0.01–35 A. Use the continuous load, not an ESD or surge peak.
Ounce presets use approximately 35 µm per oz/ft². Confirm the actual minimum finished copper with your fabricator.
10–100 °C above the local baseline.
Ambient or pre-heated board baseline.
One uniform conductor. The return path is not automatically included.
Add a voltage-drop constraint
Blank = thermal estimate only. With a budget, width uses the larger requirement; current uses the lower limit.

Load an example:

Both layer results use the same entered copper thickness. Recalculate separately if your inner and outer finished copper differ.

Outer vs. inner layer

Enter your dimensions to begin.

Results appear after calculation. No measurement or compliance approval is implied.

Calculations run in your browser. Downloading does not submit an inquiry.

Legacy estimate, not an IPC-2152 solver

This tool uses a traditional IPC-2221 curve fit and an ideal rectangular copper conductor. It does not model your stackup, copper planes, neighboring heat sources, vias, thermal reliefs, airflow, or enclosure. A result is a starting point for engineering review—not a guaranteed current rating.

Read the result correctly

Three checks before routing

01 / TEMPERATURE

Rise is not ambient

A 10 °C rise above a 60 °C local baseline gives a 70 °C resistance-evaluation temperature. The tool does not solve the board’s actual equilibrium temperature. Keep laminate, connector, and component temperature limits separate.

02 / POWER DELIVERY

Heating is not the only limit

A trace can satisfy the fitted thermal curve and still lose too much voltage. Enter the drop allowed for this conductor. Calculate the return conductor and connections separately when assessing the complete supply loop.

03 / FINISHED GEOMETRY

Use the weakest section

Check minimum finished copper, etching tolerance, pad exits, and neck-downs. A wider main route does not automatically qualify a narrow section. Vias and plane connections require their own assessment.

Why are the layer estimates different?

The two coefficients in this legacy fit produce different answers. They are not a universal rule that every inner layer must run hotter. Real heat flow depends on the surrounding board and copper. IPC-2152 addresses conductor sizing with a broader treatment of board construction and environment; those adjustments are not implemented here.

Transparent calculation

Equations, units & limits

Thermal screening and DC voltage-drop calculations are separate models. The combined result satisfies both mathematical constraints at the stated evaluation temperature, without adding a manufacturing or reliability margin.

Thermal curve fit

I = k × ΔT0.44 × A0.725
A = [I / (k × ΔT0.44)]1/0.725
W = A / t

I is in amperes, ΔT is in °C, and A is in square mils—not circular mils. Width W and thickness t are in mils for this equation. The coefficients are 0.048 for external layers and 0.024 for internal layers.

Formula reference: Texas Instruments SNVA766, section 11. 1 mil = 0.0254 mm = 25.4 µm.

Coverage checks

This tool restricts the thermal calculation to 10–100 °C rise and approximately 0.5–3 oz copper. It withholds layer results requiring more than 400 mil width or yielding a thermal current above 35 A, instead of silently extrapolating.

These upper coverage limits are documented in the AdvancedPCB legacy-calculator FAQ. Being inside them does not validate a specific board. Other input limits are software guardrails, not safety ratings.

Resistance & voltage drop

Teval = Tbaseline + ΔT
R20 = ρ20 × L / (W × t)
R(T) ≈ R20 × [1 + α × (Teval − 20)]
Vdrop = I × R(T)
Ploss = I² × R(T)

The DC model uses ρ20 = 1.7241 × 10−8 Ω·m and α = 0.00393/°C, with all geometry converted to meters. Dimensions are treated as fixed; thermal expansion, plating variation, and AC effects are neglected.

References: TI DN-71: copper PCB resistance and NBS Handbook 100: copper constants.

Optional drop constraint

Width mode: W = max(Wthermal, Wdrop)
Current mode: I = min(Ithermal, Vbudget / R(T))

Wdrop is obtained by rearranging V = IR at Teval. The actual temperature can be lower when voltage drop sets the result. No self-consistent thermal iteration is performed.

Copper presets use rounded nominal values: 17.5, 35, 70, and 105 µm. See PCBWay’s copper-weight explanation. Use the custom thickness field when your agreed finished copper differs.

From estimate to hardware

Validate the complete power path

A continuous trace is only one part of a board-level current path. Use this checklist when moving from an estimate to a released layout.

Review the layout

  • Stackup and surroundings: account for plane proximity, copper distribution, neighboring hot devices, and board mounting.
  • Transitions: review vias, thermal-relief spokes, pad entries, connectors, and every change in cross-section.
  • Manufacturing: agree minimum finished copper, etch tolerance, width/spacing rules, and inspection criteria.

IPC’s The Value of IPC-2152 discusses the influence of board construction and copper planes on conductor heating.

Review the operating case

  • Worst-case load: separate continuous current from startup, overload, fault, and switching ripple.
  • Voltage delivery: include return routing, contact resistance, cables, and the minimum voltage required at the load.
  • Temperature evidence: verify a representative assembly at worst-case ambient, load, enclosure, and cooling conditions.

This is not a fuse, creepage/clearance, impedance, pulse-current, or safety-critical conductor qualification calculator.

Common questions

PCB trace sizing FAQ

Is this an IPC-2221 or IPC-2152 calculator?

The thermal calculation is a legacy IPC-2221 curve fit. It is not an IPC-2152 implementation and does not apply stackup, board-thickness, plane, airflow, or enclosure correction factors. Use appropriate engineering analysis and measurements for the real assembly.

How much current can a 1 mm trace carry?

There is no single rating. Choose “Calculate current from width,” enter 1 mm, and specify copper thickness and permitted temperature rise. The tool compares two legacy layer curves. If you enter a voltage-drop budget, the lower of the thermal and DC drop limits is shown.

Does 2 oz copper carry twice the current of 1 oz?

Not in this thermal fit. At fixed width and allowed rise, doubling thickness multiplies the thermal current estimate by 20.725, approximately 1.65. At the same temperature and geometry apart from thickness, resistance halves. A voltage-drop-limited result can therefore scale differently.

Why does changing trace length not always change the width?

Length is absent from this simplified thermal curve. It does affect DC resistance, voltage drop, and loss. If a drop budget is entered and becomes the controlling constraint, a longer route needs a wider trace. Short heat-sunk connections are outside the assumptions of a uniform long-trace approximation.

Can I use this for switching, pulsed, or RF currents?

Not as a complete design check. RMS current relates to resistive heating when resistance is known, but pulse duration, thermal time constants, peak stress, skin effect, and proximity effect can matter. This tool assumes continuous DC and does not calculate these effects or fault survival.

Should I round the calculated width?

Width readouts round upward, but no process tolerance or design margin is added. Select a manufacturable geometry, allow for minimum finished width and thickness, and rerun the current-capacity mode with that geometry. Do not round a required width downward.

Does the tool include both supply and return traces?

No. Length means the conductor you entered. Evaluate a different return geometry separately and add its voltage drop. You may combine lengths only when the assumed width, thickness, current, and evaluation temperature are the same; this does not model thermal interaction between traces.

Why is a layer result marked “Outside range”?

The legacy graph coverage is limited. A calculated width above 10.16 mm or a thermal current above 35 A is withheld here, including in the comparison table. For high-current paths, heavy copper, planes, or unusual cooling, use an appropriate board-specific method rather than extrapolating this fit.

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