YURUNOX · Ethernet architecture & component selection
Ethernet PHY vs Switch vs Controller
A PHY operates the physical link, a controller gives a host the MAC and frame-data path, and a switch forwards frames among multiple ports. These functions can share one package, so choose from the packet path, interfaces and software model—not the marketing noun or port-speed headline.
Choose the missing job, not a familiar label
An embedded endpoint normally needs one host-facing frame engine and one physical-link path. A forwarding node needs a MAC and physical-link function per active port plus a switch core. The package boundaries vary.
| Block | Primary job | Common connections | It does not automatically provide |
|---|---|---|---|
| Ethernet PHY | Translate between a digital MAC-side interface and the medium-dependent signal; establish and monitor the link | MII, RMII, RGMII, SGMII or another digital interface; MDI toward copper, fiber or single-pair Ethernet; often MDIO management | Host DMA, packet memory, sockets, multi-port forwarding, magnetics or a connector |
| Controller or MAC | Let a processor transmit and receive frames; often adds buffers, DMA, filtering, interrupts or a host bridge | Internal system bus, PCIe, USB, SPI or memory on the host side; external PHY interface or integrated PHY on the network side | An integrated PHY, TCP/IP offload, switch fabric, driver or cable interface unless explicitly stated |
| Ethernet switch | Learn, forward, filter, queue, flood or mirror frames among ports according to Layer 2 rules | Several port MACs, integrated/external PHYs, CPU or cascade port; a separate management path | A host endpoint controller, PHY on every port, IP routing or a complete management software stack |
On narrow screens, scroll the table horizontally.
Fast rule: an existing MAC usually needs a PHY; a host without a MAC needs a controller or MAC-PHY; multiple ports that forward locally need a switch. Then confirm which PHYs and host-data interfaces are actually integrated.
Draw the frame path and management path separately
On transmit, software prepares data, the controller moves and formats the frame, the PHY creates the specified medium signal, and media circuitry connects it to the cable. A switch inserts a forwarding decision between ingress and egress port MACs.
Microchip AN1120 explains the MAC, PHY, MII, management and MDI boundaries. A link LED mainly reports a physical result; it does not prove that DMA descriptors, VLANs or IP software are correct.
What each block actually contributes
PHY: the physical-link specialist
The PHY encodes and drives the selected Ethernet medium, receives and recovers data, and participates in link establishment. Features such as auto-negotiation, diagnostics, polarity correction, master/slave behavior or low-power modes depend on the PHY and Ethernet variant.
Its digital boundary connects to a MAC. Its medium-dependent interface connects to the circuitry specified for copper, fiber, backplane or single-pair Ethernet. It does not normally allocate host descriptors or decide that a destination MAC address should leave switch port 3. TI’s PHY selection guide distinguishes the MAC-side digital domain from the MDI.
Controller: the host’s frame-data path
A MAC creates and interprets Ethernet frames. The surrounding controller may add packet FIFOs, descriptor DMA, interrupts, checksum assistance, timestamps, a PCIe or USB bridge, packet SRAM, an integrated PHY, or protocol offload.
The term is broad. The ENC28J60 integrates an SPI interface, packet memory, MAC and 10BASE-T PHY. The W5500 adds an integrated 10/100 MAC/PHY, 32 KiB buffer memory and a hardwired IPv4 socket model. Neither architecture should be treated like an MCU’s raw MAC/DMA peripheral.
Switch: local multi-port forwarding
A switch learns source addresses, looks up destinations and applies VLAN, port-state, queueing and security rules before selecting egress ports. A CPU port can carry selected frames or management traffic, but the data path must be connected and supported by the host.
A switch is not automatically a router. A management IP address only proves that the device can be managed through IP; it does not mean every forwarded frame receives a Layer 3 routing decision.
Real devices prove that product names are not integration boundaries
| Official example | Integrated blocks | External boundary | Decision consequence |
|---|---|---|---|
| STM32F2 Ethernet peripheral | MAC and dedicated DMA inside the MCU | MII or RMII to an external PHY | An MCU feature table saying “Ethernet” does not create a cable port. |
| Microchip LAN7430 | PCIe endpoint, Ethernet MAC, DMA and Gigabit copper PHY | PCIe host side; MDI toward external media circuitry | The controller includes the PHY but still does not imply magnetics or a connector. |
| Microchip LAN7431 | Related PCIe Ethernet controller without the LAN7430’s integrated copper PHY boundary | MII/RGMII for an external PHY or compatible subsystem | Related names and a common controller category can require different BOMs. |
| Microchip KSZ9477S | Seven-port Layer 2 switch with several integrated Gigabit PHYs and CPU/cascade options | Port-specific copper and digital interfaces | Count which ports include PHYs; do not equate seven switch ports with seven integrated copper PHYs. |
| NXP SJA1105 | Five-port store-and-forward switch core | Every cited port can be configured for MII, RMII or RGMII to processors, switches or external PHYs | A complete switch board may still require a separate PHY for every media port. |
Review the current official ordering code, revision, errata and supported software before design approval. These examples have different roles, speeds and grades.
MII-family names describe internal data interfaces—not the cable
| Interface | Main job | What must match |
|---|---|---|
| MII | Parallel 10/100 frame-data interface | Speed modes, I/O voltage, transmit/receive clocks, pins and timing |
| RMII | Reduced-pin 10/100 interface | 50 MHz reference-clock source/direction, timing, straps and I/O voltage |
| RGMII | Reduced-pin 10/100/1000 parallel interface | Version, clock-delay ownership, skew, trace matching, voltage and timing across temperature |
| SGMII | Serial MAC–PHY or subsystem interface | Compatible SerDes, reference clocks, in-band status, AC coupling and configuration |
| MDIO/MDC | Register management and link status | Address straps, register model, pullups, clock, reset and driver |
RGMII traces do not connect directly to 1000BASE-T cable pairs, and SGMII is not automatically an optical port. A successful MDIO read does not prove that the payload interface works. A live link does not prove that the MAC and host driver can receive a frame.
Magnetics and the connector remain separate choices
For conventional isolated twisted-pair Ethernet, the PHY’s MDI normally connects through a specified transformer network before the cable connector. A MagJack can combine transformer and connector, but it is still not the PHY. Use the exact PHY reference schematic for magnetics, center taps, termination, protection, chassis-ground strategy and layout; a transformer selected only by turns ratio can fail signal-integrity, EMC or isolation requirements.
Interactive architecture selector
This planning aid identifies the likely missing block. It does not replace a datasheet review or throughput qualification.
What does the host already have, and what must the product do?
Likely starting architecture
MAC/DMA + external PHY
CPU memory → MAC/DMA → RMII/RGMII → PHY → specified media circuit
Verify clock direction or delay mode, I/O voltage, MDIO, reset/straps, magnetics, connector, driver and compliance plan.
The result assumes ordinary Ethernet frame traffic. Protocol offload, TSN, safety, security, PoE, deterministic latency and aggregate throughput can change the architecture.
Two illustrative failures expose the boundary
Illustrative scenario · not a customer project
“The MCU has Ethernet,” but the prototype has no link
The schematic routes MCU RMII pins toward an RJ45 without a PHY. The missing function is physical signaling: RMII is a digital MAC–PHY interface and cannot directly create 100BASE-TX cable waveforms.
Evidence to check: the MCU block diagram ends at MAC/DMA and MII/RMII. Corrective direction: select a compatible PHY and add its clocks, management, reset, straps, power, magnetics, termination, protection and driver. The buyer question is “Which blocks are integrated?” rather than “Does the MCU list Ethernet?”
Illustrative scenario · not a customer project
SPI can configure the switch, but the CPU cannot send frames
Firmware reads switch registers over SPI, yet the CPU never appears as an endpoint. The likely mistake is treating the management bus as the normal data path. If the switch’s CPU port is RGMII, the processor still needs a compatible MAC and correctly timed RGMII connection.
Evidence to check: separate arrows in the switch block diagram for management and CPU-port data. Corrective direction: connect and configure the host-data port, support any required switch tagging, or select a switch/controller architecture with a compatible host frame interface.
Troubleshoot one functional boundary at a time
Changing PHY registers, MAC drivers and IP settings together destroys useful evidence. TI’s DP83822 troubleshooting guide starts with schematic/layout, power and device health, then narrows the fault. Apply the same boundary method to other devices using their own limits.
| Symptom | Likely boundary | Check before replacing silicon |
|---|---|---|
| No link | PHY power, clock, reset, straps, MDI, magnetics, cable or partner | Supplies, reference clock, reset/strap timing, PHY status, approved cable/partner and supported loopbacks |
| Link up, no frames in RAM | MAC–PHY data interface, MAC mode, pin mux, DMA or driver | Link speed versus MAC speed, RMII/RGMII clocks, counters, descriptors, interrupts and internal loopback |
| One direction fails | TX/RX timing, filters, queue or one half of the digital interface | Directional clocks/signals, error counters, receive filters and staged PHY/MAC/external loopbacks |
| Switch floods or CPU misses traffic | MAC table, VLAN, port state, tagging or CPU-port configuration | Learned addresses, VLAN/port tables, counters, ingress/egress capture and host tagging |
| Intermittent link in EMC testing | Physical layout, magnetics, protection, clock or power integrity | Exact reference layout, return paths, supplies, clocks, magnetics and compliance measurements |
Qualify the complete architecture and orderable part
- Define the network role and every port.List endpoint, bridge or router role; speed, medium, reach, isolation, PoE, environment and simultaneous traffic.
- Inventory integrated blocks.Confirm MAC, DMA, PHY, switch fabric, packet memory, host bridge, offload, magnetics and connector separately.
- Match both ends of every interface.Record clock ownership, I/O voltage, delay mode, SerDes behavior, reset, straps and management address.
- Plan the software model.Name the MAC, PHY and switch drivers, tagging protocol, VLAN model, DMA or socket ownership, boot configuration and diagnostics.
- Check the media implementation.Use the exact reference schematic for supplies, routing, magnetics, protection, connector and compliance tests.
- Approve the complete suffix.Verify package, temperature grade, qualification, lifecycle, errata, maintained drivers and allowed alternatives.
A useful RFQ includes the target host, port count, speeds, media, available data interfaces, management interface, software environment, operating grade, current part numbers and permitted alternate boundaries. “Gigabit Ethernet chip” is not a sufficient requirement.
For sourcing review, see YURUNOX’s quality-assurance approach, purchasing process, and the verified brand pages for Texas Instruments, STMicroelectronics and Broadcom.
Ethernet PHY, switch and controller FAQs
Is an Ethernet PHY the same as an Ethernet controller?
No. A PHY operates the physical link. A controller gives a host a frame data path and normally contains a MAC plus buffers, DMA or a host-bus interface. Some controllers integrate a PHY, so inspect the block diagram rather than treating the names as package definitions.
Does an Ethernet switch contain PHYs?
It may integrate several PHYs, but not necessarily one for every port. Other ports may expose RGMII, SGMII or another digital interface for an external PHY, processor, optical module or cascaded switch. Count switch ports and integrated PHYs separately.
Can a basic PHY connect directly to an MCU over SPI?
A basic PHY normally carries frame data to a MAC through an MII-family interface and uses MDIO for management. An SPI Ethernet controller or MAC-PHY can connect to an MCU over SPI because it adds controller logic, packet buffering and a defined host-data protocol.
What is the difference between MII and MDIO?
MII and its variants carry transmit and receive frame data, clocks and control. MDIO and MDC read status and configure management registers. Successful MDIO access does not validate the frame-data interface, magnetics or cable path.
If an MCU has an Ethernet MAC, does it still need a PHY?
Usually yes, unless the selected MCU or module explicitly integrates the required PHY. MII, RMII or RGMII pins are digital MAC-side interfaces. Verify the block diagram, package pinout and reference schematic.
Can an Ethernet switch replace a router?
Not by itself. A conventional Layer 2 switch forwards Ethernet frames within bridging domains. A router makes Layer 3 IP forwarding decisions between networks. Some products integrate both functions, but a switch management IP address does not prove routing capability.
Why can link be up while ping still fails?
Link-up mainly proves that the physical partners established a link. Ping also depends on MAC timing, DMA, descriptors, frame filters, VLANs, ARP, IP configuration, firewall policy and the protocol stack. Continue debugging above the PHY boundary.
Which MAC-to-PHY interface is best?
There is no universal best choice. RMII saves pins at 10/100 Mb/s, RGMII supports Gigabit Ethernet with demanding parallel timing, and SGMII reduces pins through compatible SerDes. Choose by speed, pins, voltage, timing, routing, EMC, software and component support.
Technical sources
- Microchip AN1120 — Ethernet Theory of Operation: MAC, PHY, MII, management and MDI boundaries.
- Texas Instruments — Ethernet PHY Basics and Selection Process: PHY domains and MII-family selection.
- STMicroelectronics RM0033: an MCU MAC/DMA with MII/RMII to an external PHY.
- Microchip LAN7430/LAN7431 datasheet: related controllers with different PHY boundaries.
- Microchip ENC28J60 datasheet and WIZnet W5500 documentation: two stand-alone controller/software models.
- Microchip KSZ9477S and NXP SJA1105 datasheet: switches with integrated-versus-external PHY patterns.
- Texas Instruments DP83822 Troubleshooting Guide: boundary-based PHY application debugging.
Manufacturer examples support the integration patterns. No board simulation, throughput benchmark, EMC test or interoperability qualification is claimed for this article.