How to Select a MOSFET for Your Design

Write a one-page MOSFET stress specification

Record topology, normal and maximum bus voltage, measured or modeled drain spike, RMS current, switching current, peak and fault current, pulse duration, repetition rate, switching frequency, duty-cycle range, gate-drive voltage, dead time, ambient or coolant temperature and intended cooling. Separate repetitive operating events from rare protected faults.

• Gate 01Electrical stressVoltage, current, polarity, gate limits and transients.
• Gate 02Application lossConduction, transition, output charge and diode behavior.
• Gate 03Thermal and SOAJunction temperature and every linear or fault trajectory.
• Gate 04Hardware evidencePin-level waveforms, temperature and fault recovery.

Topology decides the weighting. A battery disconnect may be dominated by hot resistance. A high-frequency hard-switched converter may accept higher resistance for lower charge. A hot-swap element spends real time in linear mode. A motor bridge adds diode commutation, regeneration, shoot-through and avalanche questions.

Choose polarity and technology deliberately

N-channel silicon MOSFETs usually provide lower resistance for a given die size and voltage class. A low-side device is straightforward; a high-side N-channel device needs a driver that raises its gate above the moving source. A P-channel device can simplify a modest high-side switch, commonly at a resistance or die-size penalty.

Silicon, SiC MOSFETs and GaN transistors are not automatic substitutes. Their gate limits, recommended drive, reverse conduction, switching speed, parasitics, packages and fault behavior differ. Select the technology only after the operating envelope is clear.

Set voltage margin from a waveform and current from loss

V_DS must cover more than the nominal bus

The off-state drain rating must exceed the highest voltage the part will experience, including supply tolerance, transformer or cable inductance, motor regeneration, load dump, ringing and clamp tolerance. Measure fast edges with suitable bandwidth and a short probe loop. A clean simulation that omits package and PCB parasitics does not close the requirement.

Do not apply one universal rule such as 20% or 2× without explaining the underlying stress. A measured 24 V motor bus that reaches 42 V during regeneration is different from a tightly clamped 24 V converter. Choose the next suitable voltage class above the validated worst case plus a documented project allowance. Excess rating can cost resistance, charge, area or money; insufficient rating turns breakdown or avalanche into normal operation.

The front-page current number is a limit, not a board promise

A continuous-current rating can be calculated from silicon, package and assumed case-temperature limits. It does not prove that an arbitrary PCB can carry or cool that current. Calculate RMS current for conduction, switching current for transition stress, and peak current for SOA and package limits. Include inrush, stall, short-circuit delay, current-limit tolerance and current sharing.

Swipe horizontally to compare the checks.

Use R_DS(on) at the actual gate voltage and temperature

Begin with the maximum guaranteed on-resistance at a gate voltage the driver can maintain. Then use the manufacturer’s normalized-temperature curve or a qualified model to estimate hot resistance. Iterate because resistance creates loss, loss raises junction temperature and temperature raises resistance.

V_GS(th) is not the turn-on voltage

Threshold voltage is measured at a very small drain current. It describes the onset of conduction, not the gate drive needed for low resistance at load. A “logic-level” label is only useful when the datasheet guarantees acceptable R_DS(on) at your available drive, such as 4.5 V or 2.5 V.

Measure gate voltage from gate to source. A high-side gate at 12 V absolute is not receiving 12 V drive if its source has risen to 10 V; V_GS is only 2 V. Check the maximum positive and negative gate limits during startup, ringing, reverse connection and faults.

A real datasheet example: TI CSD18540Q5B

TI lists this active 60 V N-channel silicon MOSFET with maximum R_DS(on) of 3.3 mΩ at V_GS = 4.5 V and 2.2 mΩ at 10 V, both at I_D = 28 A. V_GS(th) is 1.5–2.3 V at only 250 µA. That threshold row cannot be used as the drive recommendation.

The product page also separates a 221 A silicon-limited current from a 100 A package-limited current. Neither figure proves 100 A continuous operation on the planned board. Use the exact TI product page and Rev. B datasheet to retain the conditions beside every value.

Estimate conduction, transition and temperature together

The calculator below is an engineering screen for a hard-switched silicon MOSFET. Use hot maximum resistance and edge times expected with the intended driver and layout. It deliberately keeps gate-drive demand separate from estimated MOSFET junction loss.

Read the result as a first iteration

At the defaults, conduction loss is 18² × 5.28 mΩ × 0.75 = 1.283 W. The simple overlap model gives 1.050 W of transition loss, so the partial MOSFET loss is 2.333 W. With an illustrative validated system thermal resistance of 20 °C/W and a 70 °C boundary, estimated T_j is 116.7 °C.

The 0.053 W gate-bias result is drawn from the gate-drive supply and is not added again to channel loss. Replace assumed edge times with measured or modeled values, add omitted loss, update hot resistance at the resulting temperature and repeat. Apply a reliability target below the absolute maximum junction temperature.

Lower R_DS(on) can increase the switching burden

A larger die can reduce resistance but usually increases charge and capacitance. At high frequency, that trade can erase the conduction benefit. For an early hard-switching screen:

This omits nonlinear output-capacitance energy, reverse recovery, body-diode conduction, parasitic ringing and topology-specific recovery. Soft-switching circuits require a different model. Datasheet times from a resistive test may not transfer to your gate loop and commutation path.

Swipe horizontally to compare the parameters.

Average gate-charge current is Q_g × f_SW, but this average does not size peak driver source or sink current. A fast transition requires moving the relevant charge quickly through driver resistance, external gate resistance, internal gate resistance and loop inductance.

Faster is not automatically better. Reducing gate resistance may cut transition loss while increasing overshoot, recovery stress, EMI or false turn-on. A Kelvin source, split turn-on and turn-off resistors, Miller clamp or negative turn-off bias can help in demanding designs, but each must stay within the MOSFET and driver limits.

The package is part of the switching loop

Package geometry, internal source inductance, thermal attachment and the copper footprint all affect the achieved edge and junction temperature. A footprint match is not an electrical equivalence.

Route the driver return to the device source reference, keep the gate loop compact, and measure V_GS at the device pins. If an alternate changes package construction or source connections, repeat switching, EMI and thermal validation.

A 3.3 V gate signal forced a real design change

What to copy into your own review

1. Write the minimum gate-to-source voltage available at the MOSFET pins, including driver and source movement.
2. Find a maximum R_DS(on) row at that drive voltage. Do not interpolate a guarantee from a typical curve.
3. Calculate hot resistance and loss at the current waveform.
4. If the evidence is missing, change the MOSFET, driver or operating point before layout freeze.

This is the kind of published operational detail that turns a warning into a decision. It does not prove the cited device is unsuitable at every 3.3 V condition; it shows why the exact datasheet guarantee and implementation must agree.

SOA, diode recovery and avalanche are not covered by R_DS(on)

Safe operating area matters whenever V_DS and I_D overlap

SOA plots allowable current versus drain voltage for specified pulse durations and starting conditions. It combines resistive, package-current, power, thermal and thermal-instability limits. Hot swap, e-fuses, inrush limiting, active discharge, precharge and slow gate ramps can keep the MOSFET in linear mode much longer than an ordinary edge.

Plot the entire worst-case V_DS-I_D-time trajectory, not only its endpoint. Include current-limit tolerance, output-capacitor charging, gate ramp, restart attempts and the hot initial board or case temperature. Use the curve for the correct pulse duration and manufacturer rerating guidance; do not invent a missing DC line.

The body diode changes bridge and synchronous-converter behavior

During dead time, the body diode may conduct. Its forward drop creates loss and its stored charge can create reverse-recovery current when voltage reverses. Compare Q_rr only at compatible current, di/dt, gate condition and temperature. Too little dead time risks shoot-through; too much increases diode conduction and may worsen recovery.

Avalanche rating is not a free repetitive clamp

A single-pulse unclamped inductive switching rating characterizes one event under stated conditions. It does not automatically approve repetitive avalanche for product life. If avalanche occurs normally, quantify energy, repetition, initial T_j, inductor tolerance and peak current. Use manufacturer repetitive-avalanche guidance or an external clamp when evidence is insufficient.

The package rating is only one boundary in the thermal system

R_θJA belongs to a stated test board and environment. Copper area, layer stack, vias, airflow, neighboring heat sources, interface materials and mounting determine the real thermal path. A top-side-cooled package and a bottom-exposed-pad package impose different mechanical and assembly requirements.

For short pulses, use transient thermal impedance Z_θ with the right pulse duration and duty cycle. Check whether the curve is junction-to-case, mounting base or ambient. A single-pulse curve starting from 25 °C cannot be pasted into a hot repetitive system without rerating.

Estimate T_j for steady full load, burst operation, startup, locked rotor, current limit and shutdown delay. Then compare the model with representative electrical-loss and temperature measurements. A case-temperature reading still needs an appropriate junction estimate.

Layout is part of MOSFET selection

Common-source inductance creates voltage that opposes fast current change. Kelvin-source packages separate the driver return from the high-current path, but that benefit disappears if the PCB rejoins them incorrectly. Keep the high-current switching loop compact, place the driver near gate and source return, and keep noisy power current out of sensitive control references.

Confirm footprint, pinout, creepage, source connections, thermal pad, moisture sensitivity and assembly process before approving an alternate. Package compatibility does not establish equal parasitics or cooling.

The lowest-resistance candidate may not have the lowest partial loss

At an illustrative 30 V, 20 A transition, 18 A RMS current, 0.75 conduction fraction and 100 kHz, compare two fictional candidates. Their hot resistance and achieved transition times already include the project’s driver and layout assumptions.

Swipe horizontally to compare the candidates.

Candidate A wins the resistance comparison but not this partial-loss comparison. Candidate B is only slightly lower, and adding E_oss, Q_rr, thermal behavior, EMI, cost or tolerance can reverse the result. The lesson is not to prefer B; it is to compare total behavior at the application operating point.

Swipe horizontally to compare application priorities.

Validate the exact orderable part on the intended PCB

1. Confirm the exact identity.Retain manufacturer part number, suffix, package, grade and current datasheet revision.
2. Recalculate every operating mode.Use component tolerances for normal, corner, startup and fault stress.
3. Close loss and temperature.Include conduction, transition, E_oss, diode/recovery and relevant parasitic loss.
4. Verify limits independently.Check V_DS, V_GS, current, SOA, avalanche, diode and package restrictions.
5. Probe at the device pins.Measure V_DS, V_GS, current, ringing and temperature on representative boards.
6. Exercise real sequences.Test startup, shutdown, short circuit, stall, reverse energy, open load and reset behavior that apply.
7. Repeat for every alternate.Pin compatibility does not waive loss, EMI, thermal or fault requalification.

What to include in a MOSFET RFQ

Provide topology, bus and transient voltage, RMS/switching/peak current, frequency, duty range, actual gate voltage, temperature, cooling, package, grade, quantity and lifecycle need. For alternatives, require comparison of maximum R_DS(on) at your drive, Q_g/Q_gd, E_oss/Q_oss, Q_rr, internal gate resistance, SOA, avalanche, pinout and thermal pad.

Review YURUNOX’s Texas Instruments and Infineon component resources, plus its quality assurance information. Brand or pin compatibility is only the beginning of engineering review.