YURUNOX · Ethernet architecture, qualification, and sourcing control
Broadcom Ethernet PHY Buying Guide
Choose the line-side medium first, then prove the MAC interface, timing, security, package, software, and supply path. A speed label alone is not a valid PHY selection method, and an “Active” lifecycle label is not a stock quotation.
Start outside the chip
A workable Broadcom Ethernet PHY is the device that matches the cable and Ethernet standard on one side and the processor or switch MAC interface on the other. After that electrical fit is proven, compare port count, PTP or SyncE, MACsec, package, temperature grade, driver support, lifecycle status, and real supply availability.
Write one line before searching: “We need [line standard] over [medium], [port count], connected to [host interface], with [timing/security], in [package/temperature].” If one field is unknown, the part number search is premature.
A PHY is not a switch or an Ethernet controller
The PHY handles the physical signaling at the network edge. The MAC frames the data. A switch moves frames among ports. Some SoCs integrate a MAC, some devices integrate both MAC and PHY, and some boards need a discrete PHY between an existing MAC and the connector or transformer network.
Buy a PHY when
Your processor or switch already provides a compatible Ethernet MAC but still needs the analog line interface and link functions.
Buy a switch when
You must connect and forward traffic among multiple Ethernet ports. A switch may contain MACs and PHYs, but its job is broader.
Recheck the architecture when
The host has no Ethernet MAC, the proposed host interface is incompatible, or a module already integrates the required PHY.
Choose the line-side Ethernet family before a model
“Ethernet PHY” covers electrically different channels. A familiar RJ45 copper design, an automotive single-pair link, and a PAM4 optical design are not interchangeable branches of one generic BOM.
| Link family | Typical medium | First requirement to lock | Broadcom path to investigate | Common purchasing mistake |
|---|---|---|---|---|
| 10/100/1000BASE-T | Four-pair twisted copper, commonly RJ45 through magnetics | 10/100/1000 rate set and host-side RGMII or serial interface | BCM5421x single-port or BCM5424x/5428x multiport families | Comparing only “Gigabit” and overlooking RGMII versus SGMII |
| 2.5G / 5G / 10GBASE-T | Multi-pair copper | Negotiated rate set, USXGMII/XFI/BASE-X host path, thermal budget | BCM8488x/8489x single-port or BCM8491x multiport families | Dropping a 10G PHY into a design whose host cannot carry the rate |
| 100/1000/2.5G/5G/10GBASE-T1 | Automotive single twisted pair | Automotive standard, EMC, diagnostics, qualification, safety and security needs | BCM898xx automotive PHY families | Treating BASE-T1 as ordinary RJ45 BASE-T because both use copper |
| Optical high speed | Optical module or direct optical architecture | Lane rate, modulation, FEC, module interface, power and thermal design | BCM87xxx optical PHY/DSP portfolio | Using a copper-PHY checklist for a PAM4 optical link |
Representative Broadcom PHYs—and what each example teaches
This is a navigation shortlist, not a drop-in substitution list. Product status and distributor-inventory indicators below were checked on Broadcom’s public product pages on August 28, 2026; buyers should recheck the current page, ordering code, errata, and product brief before release.
| Example | Line side / ports | Host-side clues | Package / key functions | Public-page signal when checked | Buyer takeaway |
|---|---|---|---|---|---|
| BCM54213PE | 10/100/1000BASE-T, 1 port | RGMII | 36-pin QFN; EEE, WoL, cable diagnostics, integrated regulator | Active · inventory Yes | A compact single-port option when RGMII is already fixed |
| BCM54210 | 10/100/1000BASE-T, 1 port | RGMII or SGMII | 64-pin QFN; IEEE 1588v2, SyncE, EEE, diagnostics | Active · inventory Yes | Same headline rate, but a different interface and timing proposition |
| BCM54240 | Gigabit copper/fiber, 4 ports | SGMII | Quad PHY; timing-oriented features | Active · inventory No | Port density and serial host aggregation may matter more than single-port simplicity |
| BCM84891L | 100M/1G/2.5G/5G/10GBASE-T, 1 port | USXGMII, XFI and selected BASE-X modes | 8 × 8 mm BGA | Active · inventory No | Multi-rate copper requires host bandwidth and thermal proof, not merely a 10G label |
| BCM84918 | Multi-rate 10GBASE-T, 8 ports | High-density serial host architecture | 17 × 17 mm FCFBGA; octal integration | Active · inventory No | High density changes power, escape routing, cooling, firmware and supply risk together |
| BCM89811 | 100BASE-T1, 1 automotive port | RGMII | 6 × 6 mm package; automotive single-pair use | Active · inventory No | A 100 Mb/s automotive PHY is selected around a different channel and qualification context |
| BCM89890 | 2.5G/5G/10GBASE-T1, 1 automotive port | XFI or PCIe-oriented connection | MACsec AES-128/256, PTP/802.1AS; AEC-Q100 | Active · inventory No | At automotive multigig rates, security, timing, qualification and interface architecture converge |
Important naming check: Broadcom’s public URL for the BCM89811 page currently ends in “bcm89881,” while the page heading and device content identify BCM89811. Record the device name and the exact ordering code from controlled documentation; never infer a part number from a URL slug.
BCM54213PE vs BCM54210: “single-port Gigabit” is not enough
Both public pages describe active, single-port 10/100/1000BASE-T devices. That similarity is where weak shortlists stop. The meaningful differences start one layer deeper.
Compact RGMII path
- RGMII host interface
- 36-pin QFN footprint
- EEE, Wake-on-LAN and cable diagnostics
- Integrated regulator can simplify a board-level power tree
Interface and timing flexibility
- RGMII or SGMII host interface
- 64-pin QFN footprint
- IEEE 1588v2 timestamping-oriented capability
- SyncE support plus EEE and diagnostics
Procurement consequence: even if both devices are available, substituting one for the other can require a new PCB footprint, new interface configuration, different clocking assumptions, and a new software-validation cycle. “Same speed and port count” is not equivalence.
The package is part of the electrical decision
A smaller QFN may help area and cost, but it changes routing, thermal-pad design, assembly controls, inspection visibility, and rework difficulty. A BGA can enable higher density and speed while demanding tighter escape routing and X-ray inspection capability.
Ask for the full ordering code and package drawing. Then verify pinout, exposed-pad requirements, moisture-sensitivity level, tray or reel format, minimum order quantity, and whether your assembler has an approved stencil and reflow profile for that package.
Prove the MAC-side interface and clocking path
The host interface is not a cosmetic feature. It determines pin count, signaling rate, clock topology, PCB constraints, driver configuration, and whether the MAC can exchange data at the promised line rate.
| Interface | What it usually signals | Buyer checks | Typical failure mode |
|---|---|---|---|
| RGMII | Parallel reduced-pin Gigabit MAC interface | I/O voltage, internal/external delays, clock direction, PCB skew budget, host support | Link comes up but traffic is unstable because delay assumptions differ |
| SGMII | Serial Gigabit-class MAC/PHY connection | SerDes capability, reference clock, in-band status, autonegotiation behavior | A host with only parallel RGMII cannot connect without architectural change |
| QSGMII | Four Gigabit channels over a compact serial link | Port mapping, lane aggregation, host switch support, firmware configuration | Multiport density is selected before checking that the switch fabric exposes QSGMII |
| USXGMII | Multi-rate serial interface for 10M through multigig/10G use cases | Supported rate set, SerDes speed, negotiation, firmware, reference clock | “Supports 10G” is assumed to mean all intermediate rates and modes work automatically |
| XFI / BASE-X | 10G-class or encoded serial host/line interfaces | Exact mode, lane rate, FEC and PCS expectations, electrical compliance | Two interfaces share a connector or lane speed but not the same protocol role |
The host has RGMII; the proposed PHY is USXGMII-first
The part may have the desired 5G or 10G copper capability, yet the board cannot use it directly. The correct response is not an adapter assumption. Reopen the SoC or FPGA architecture, available SerDes lanes, clocking, firmware support, and bandwidth requirement.
RGMII timing is “fixed in layout” but not in the configuration
Some MAC/PHY combinations add transmit or receive delay internally; others expect PCB trace delay. If both add it—or neither does—the design can become temperature- and board-dependent. Put the delay mode in the schematic notes and software bring-up checklist.
Translate feature names into system requirements
Energy Efficient Ethernet
IEEE 802.3az EEE reduces energy during low utilization. Confirm that the peer, operating system, power target, latency behavior, and validation plan support enabling it; do not treat the acronym as free savings.
PTP / IEEE 1588
Hardware timestamp support can improve time accuracy, but the complete path includes MAC, driver, timestamp queue, oscillator, board clocking, firmware and the application’s synchronization profile.
Synchronous Ethernet
SyncE distributes frequency through the physical layer. Check recovered-clock pins, jitter performance, clock-tree integration, device mode, and telecom profile rather than searching for “SyncE” alone.
MACsec
MACsec can protect Layer 2 traffic, but a secure design must define cipher strength, key management, throughput, latency, controlled ports, software integration, and certification needs.
Cable diagnostics
Pair-fault and cable-length diagnostics can speed service, but register behavior, accuracy, link-state restrictions, test modes, and driver exposure vary. Obtain the programming documentation before promising a field feature.
Wake-on-LAN
WoL is a platform function. Verify standby rail availability, PHY low-power mode, magic-packet behavior, MAC or controller handoff, and system wake logic.
“Active” does not mean “available from distribution”
This comparison uses Broadcom’s own public status and distributor-inventory fields. It is not a YURUNOX shipment story, customer result, or claim about guaranteed supply.
Active + inventory Yes
When checked, the BCM54213PE and BCM54210 pages showed “Active” and “Distributor Inventory: Yes.”
What the evidence supports: lifecycle and channel visibility are separate fields. “Active” indicates a manufacturer lifecycle state; it does not quote your quantity, date code, lead time, price, allocated supply, packaging, or authorized source.
What a buyer should do: request an offer tied to exact manufacturer part number, quantity, required delivery date, source type, traceability, date/lot-code policy, packaging, inspection plan, and quote validity. Recheck the manufacturer page because public fields can change.
Treat power, thermal design, and external circuitry as selection inputs
Power-tree questions
- Which core, analog, I/O, and standby rails are required?
- Is a regulator integrated, and what external components remain?
- What is worst-case power in each rate and temperature condition?
- What power-up, reset, strap-latch, and clock sequence applies?
- Can the board sustain low-power, WoL, or EEE modes correctly?
Line-side and assembly questions
- Which magnetics or coupling network is qualified for the exact PHY?
- What surge, ESD, common-mode and EMI design is required?
- Does the package escape within the board stack-up and via rules?
- Is exposed-pad or BGA thermal performance adequate?
- Can manufacturing inspect, rework, bake, and store the package?
Cost reality: compare total implementation cost, not unit price alone. A cheaper PHY that requires an extra regulator, more layers, a larger footprint, licensed firmware, or a new validation cycle may increase the finished-board cost.
A repeatable Broadcom PHY selection process
Define the physical channel
Name the IEEE link family, medium, reach, connector/coupler, cable category, EMI environment, isolation and surge expectations.
Freeze speed and port count
List every required negotiated rate—not only the maximum—and decide single, quad, octal, or other port density.
Match the host interface
Verify the MAC/SerDes mode, I/O voltage, lane count, rate, reference clock, delay mode, autonegotiation behavior and pin mux.
Translate system features
Convert PTP, SyncE, EEE, MACsec, diagnostics and WoL into testable system requirements and software ownership.
Close the board design
Check package, pinout, straps, power rails, thermals, magnetics/coupling, EMI protection, layout guidance and manufacturing capability.
Close the software path
Confirm driver availability, register documentation access, firmware or patch needs, boot configuration, diagnostics API and change-control process.
Qualify the supply path
Validate lifecycle, exact ordering code, approved vendor, lead time, traceability, date/lot policy, packaging, inspection, alternates and last-time-buy exposure.
Build a defensible search path
This tool identifies the next evidence to collect. It does not certify compatibility or recommend a drop-in replacement.
Start with the channel
Select the channel, rate, and known host interface, then build a verification path.
What to put in the RFQ—and what to inspect on receipt
RFQ evidence package
- Exact Broadcom manufacturer part number and acceptable suffixes
- Quantity, target price, requested ship date and destination
- New/unused condition, source type and traceability requirement
- Date-code and lot-code acceptance rules; mixing restrictions
- Tray, tube or tape-and-reel format and minimum pack quantity
- RoHS/REACH and automotive or other compliance evidence
- Inspection, electrical-test and nonconformance terms
Receiving and engineering checks
- PO, packing list, label, reel/tray and device marking consistency
- Package dimensions, pin-one orientation and marking quality
- Moisture-barrier bag, desiccant, humidity indicator and MSL handling
- Lot/date traceability and evidence appropriate to the source risk
- Sample X-ray or enhanced inspection when BGA/source risk justifies it
- Board bring-up: ID registers, link modes, BER/traffic and temperature
- Feature tests for PTP, SyncE, EEE, MACsec, diagnostics or WoL as applicable
YURUNOX is an independent electronic-component sourcing partner, not Broadcom or a semiconductor manufacturer. For a sourcing review, share the full ordering code, quantity, application, target delivery date, host interface, required traceability, and whether alternates are allowed. See the Broadcom sourcing page and quality-assurance process.
Four shortcuts that create expensive redesigns
“Both are Gigabit, so they are equivalent”
Speed does not prove interface, package, timing, power, register, magnetics, temperature or software compatibility. Build a pin-and-function equivalence matrix before discussing substitution.
“Active means we can buy it now”
Lifecycle status is not an offer. Capture seller, stock position, lead time, quote validity, source authorization, traceability and required delivery in the commercial review.
“Automotive Ethernet is ordinary Ethernet with a rugged cable”
BASE-T1 uses a different physical channel and adds automotive EMC, qualification, diagnostic, safety, temperature and supply expectations. Run it as a distinct architecture.
“The driver can be handled after layout”
Register access, boot straps, firmware patches, timing control and diagnostic APIs can determine whether the device is usable. Assign software ownership before PCB release.
Broadcom Ethernet PHY questions
How do I choose a Broadcom Ethernet PHY?
Lock the line-side Ethernet standard and medium first, then the host MAC interface, required rate set, port count, timing/security features, package, temperature, software support, lifecycle and supply evidence. Do not begin with a model number or maximum speed alone.
What is the difference between an Ethernet PHY and an Ethernet switch?
A PHY converts between digital MAC-side data and the electrical or optical physical link. A switch learns addresses and forwards Ethernet frames among ports. A switch may integrate PHYs, but the two functions are not interchangeable.
Can I replace one Gigabit Ethernet PHY with another?
Only after proving pinout, package, host interface, timing, voltage, magnetics, power, thermal, register, driver, compliance and feature equivalence. Matching 10/100/1000 speed and port count is insufficient.
What is the practical difference between RGMII and SGMII?
RGMII is a reduced-pin parallel MAC interface with explicit clock-and-delay concerns. SGMII is a serial interface that requires compatible SerDes, clocking, negotiation and in-band-status behavior. A host that exposes one does not automatically support the other.
Does Broadcom “Active” status mean the PHY is in stock?
No. “Active” is a lifecycle indicator, while distributor inventory, lead time, quantity, packaging and source availability are separate. Request a current, time-bounded quotation for the exact ordering code and required quantity.
When do I need PTP, SyncE, EEE, or MACsec?
Choose PTP when the system needs precise time alignment, SyncE when frequency distribution is required, EEE when low-utilization energy matters, and MACsec when Layer 2 link protection is part of the security architecture. Each feature must be supported by the complete hardware and software path.
Is BASE-T1 compatible with ordinary RJ45 BASE-T Ethernet?
No. Automotive BASE-T1 uses a single-pair physical channel and different coupling, EMC and qualification assumptions. It may carry Ethernet frames, but the PHY and line-side hardware must match the relevant BASE-T1 standard.
What information should I send with a Broadcom PHY RFQ?
Send the full manufacturer part number, quantity, target delivery, destination, application, host interface, acceptable date/lot codes, packaging, traceability and compliance requirements, plus whether alternates or different suffixes are permitted.
Verify against controlled documentation
Public portfolio pages are useful for discovery. Final design and purchase approval should use the latest applicable product brief, datasheet, package drawing, errata, software documentation, lifecycle notice, and written supplier offer.
- Broadcom PHY and PoE portfolio
- Broadcom copper PHY portfolio
- Broadcom Gigabit Ethernet PHY catalog
- BCM54213PE product page
- BCM54210 product page
- BCM84880 product brief
- BCM84891L product page
- BCM84918 product page
- Broadcom automotive Ethernet portfolio
- BCM89890 product page
- BCM87800 optical PHY product page
- IEEE 802.3bz 2.5G/5GBASE-T project
- IEEE 802.3az Energy Efficient Ethernet project
Need a Broadcom PHY sourcing and risk review?
Send the exact ordering code and design constraints. YURUNOX can review source visibility, traceability, packaging, date/lot requirements, inspection needs, and commercially viable alternatives without treating headline speed as equivalence.
Independence and scope: YURUNOX is an independent sourcing partner and is not affiliated with or endorsed by Broadcom. Broadcom and product names are the property of their respective owners. Representative products are examples for selection logic, not compatibility guarantees. Third-party images are licensed and credited at their point of use.