EEPROM vs NOR Flash vs FRAM: Which Memory Fits?

The useful comparison is the write workload

A calibration value changed during service, a firmware image read at boot and a counter saved ten times per second are three different jobs. Choosing memory only by capacity or price hides the firmware and reliability work that follows.

On narrow screens, scroll the table horizontally.

There is no useful universal “cheapest memory” ranking. Compare the part, extra board area, firmware, qualification effort and field-recovery requirements at your actual capacity and volume.

What changes when you write a byte?

EEPROM: easy small updates, with a wait afterward

EEPROM means electrically erasable programmable read-only memory. Despite the historical name, it is rewritable. With a typical serial EEPROM, the host sends an address and data; the device then performs a self-timed internal write.

The driver must respect the page boundary and wait until the part is ready. For the 24LC256, sending a page write past the boundary can wrap within that page instead of continuing into the next one. ACK polling checks readiness without assuming that every write takes the maximum time. Microchip’s EEPROM application guide explains these driver-level details.

NOR Flash: program a small region, reclaim a larger one

NOR programming normally changes bits from 1 to 0; erasing restores them to 1. A program page and an erase sector are different units. Changing a short value may therefore require a fresh record location, followed later by copying valid data and erasing old storage.

This works well for firmware and append-based storage, but “just overwrite the variable” is not a complete NOR strategy. Execute-in-place also requires a compatible memory-mapped host controller and device configuration; having a generic SPI peripheral is not enough.

FRAM: direct overwrite, not a magic transaction

FRAM stores information using ferroelectric polarization, not magnetism. Supported serial devices can save incoming bytes without a separate erase operation or EEPROM-style internal write delay.

Data still takes time to cross the bus. If a 32-byte record is interrupted after only some bytes arrive, fast individual writes do not make the whole record complete. On FRAM architectures with read-and-restore behavior, reads also contribute to endurance. TI’s FRAM reliability report explains that distinction for its MSP430 FRAM devices.

What three actual datasheets tell you

These examples make the differences concrete. They have different densities and are not a drop-in replacement list or an equal-capacity price comparison. Check the exact ordering code, grade and applicable revision before approving a part.

Examples: Microchip DS20001203Y; Winbond Rev. M, December 24, 2024; Infineon 001-84458 Rev. *K, December 5, 2018. These are the cited documents, not a claim that every current or similarly named grade shares their limits.

Keep bits and bytes separate: an 8-KiB memory holds 8,192 bytes, not 64,000 bytes. Firmware, record headers, checksums, spare copies and recovery space all reduce capacity available to useful data.

Bus speed is not the time to a completed save

A well-designed asynchronous driver can do other work while EEPROM is busy. The important question is when the data is persistent, not whether the CPU must sit idle.

For NOR, a higher SPI clock also leaves internal program and erase time to account for. Size buffers for the longest required reclaim operation, not only the average write rate. If firmware executes from that memory, check access restrictions and any supported suspend mechanism during programming or erasing.

Count writes, storage and retention separately

Endurance is the specified cycling budget. Retention is how long stored data remains valid under stated conditions. Record integrity is whether a recovered record is complete and trustworthy. A strong number in one category does not answer the other two.

Look for the hottest location—not just total writes

Ten updates per second for five 365-day years produce about 1.58 billion logical updates. A hypothetical budget of one million cycles spent on the same endurance unit at ten cycles per second would be used in 100,000 seconds, or about 27.8 hours. This is budget arithmetic, not a claim that a particular EEPROM will physically fail after that time.

One save may change payload, a sequence counter, a checksum and a commit marker. Moving the payload while always rewriting the same “latest record” pointer leaves a hot spot. For NOR, count how often each sector is reclaimed. For FRAM, follow the part’s read/write and internal-row rules rather than treating every byte address as an independent unlimited resource.

Temperature changes the retention question

The cited industrial FM24CL64B datasheet specifies minimum retention of 10 years at 85°C, 38 years at 75°C and 151 years at 65°C. Those are different temperature conditions—not three interchangeable lifetime promises. Start with the actual powered and unpowered temperature profile, cycling history and required retention interval. See the retention table.

Assembly is a separate check. TI’s SLAA526A distinguishes its MSP430FR57xx family, which must be programmed after reflow, from the other MSP430 FRAM devices covered by that report. Do not extend one family’s programming or baking rules to every FRAM component. See TI’s reflow guidance.

Nonvolatile bytes do not guarantee an intact record

Suppose a saved record contains a sequence number, operating count and CRC. After a mid-write reset, the sequence number might be new while the count is old. The application needs a rule for rejecting that mixture and finding the last committed version.

FRAM’s short write path reduces the time exposed to interruption, but completed bytes and a completed record remain different concepts. Infineon’s F-RAM power-failure discussion describes the behavior of completed versus interrupted byte transfers; the device’s voltage and power-down requirements still apply.

1. 1 · Keep the valid versionRetain a committed record outside the candidate update’s relevant failure or erase region.
2. 2 · Write a candidateInclude version, sequence, length, payload and integrity information. Finish the required device operations.
3. 3 · Commit, then retireUse a device-qualified completion method. Recover the newest valid committed version before reclaiming the old one.

This is an architecture, not a universal two-slot recipe. The guaranteed write unit, failure region, erase geometry and commit-marker behavior determine the implementation. Two copies in the same sector are not independent protection if reclaiming that sector can remove both.

Define the acceptance rule before selecting the memory. “The newest uncommitted update may be lost, but all previously committed data must recover” is different from “no event may be lost.” The second requirement may need earlier persistence, enough hold-up energy for the entire save path, or a different system architecture. Reset supervision must keep the host and memory within their valid operating conditions.

Three practical selection scenarios

The selection lesson is straightforward: use the simplest architecture that meets the actual workload and recovery rule. A mixed-memory design can solve different jobs well, but each additional memory and transfer path adds qualification work.

Qualify the behavior before approving the purchase

Two parts with the same density, interface label or eight-pin outline can still need different firmware. A sourcing alternative is only a candidate until its electrical limits, memory organization and recovery behavior have been reviewed.

1. Write down the workload.List useful bytes, metadata, peak update rate, hot addresses, read traffic, service life and archive duration.
2. Check electrical and physical compatibility.Compare operating voltage, logic thresholds, pin assignments, package dimensions, temperature grade, startup timing and write-protect behavior.
3. Review the full driver contract.Check address width and mapping, page boundaries, command set, busy/ready handling, erase units and any restrictions on repeated partial programming or internal ECC.
4. Test persistence, not just communication.Exercise page ends, capacity ends, retries, reset timing, interrupted writes and near-full reclaim. Capture supply voltage alongside the interface signals.
5. Match the supply documentation.Specify the complete manufacturer part number, allowed alternatives, packaging, traceability and inspection requirements. Functional testing and supply-chain provenance answer different questions.

A useful RFQ states capacity after overhead, interface and clock, voltage, package, temperature range, access workload, retention conditions and the permitted loss rule. Attach the approved part number and datasheet revision. “64 Kbit memory, eight pins” leaves too much unspecified.

For supply review, see YURUNOX’s quality-assurance approach and purchasing process. Brand-specific sourcing information is also available for Infineon and STMicroelectronics.