How to Verify an IC Package Type
Do not approve a package because it “looks like QFN” or has the right pin count. Verify the complete orderable part number against the manufacturer’s exact package drawing, then confirm body dimensions, pitch, height, orientation, underside geometry, and the original receiving label.
An exact IC package is a five-way match.
Start with the complete manufacturer part number. Use the manufacturer’s ordering table to find the package designator, then open the controlled mechanical outline for that code. Confirm terminal count, body length and width, maximum height, lead or ball pitch, pin 1, exposed pad, and bottom-side map. Finally, reconcile the result with the reel, tray, tube, or moisture-barrier-bag label and receiving records.
A top-view photo can identify a likely family. It cannot by itself prove the exact package option, board footprint, or authentic origin.
Full MPN
Defines the orderable option, not just the electrical family.
Marking map
Links abbreviated top code to manufacturer-controlled data.
Official drawing
Defines dimensions, tolerance, terminals and orientation.
Physical sample
Provides measured and photographed comparison evidence.
Receiving record
Connects the claimed part to carrier, lot and source.
Define what “verified” must mean before inspecting.
A family name is sufficient for sorting a photograph, but it is not sufficient for footprint release, alternate approval, or production-lot acceptance.
| Verification level | Question answered | Evidence required | Suitable use |
|---|---|---|---|
| Family | Is it broadly SOIC, QFP, QFN, BGA, WLCSP, or another construction? | Visible lead style, terminal sides, approximate body shape. | Initial sorting and search planning. |
| Mechanical variant | Which body size, pitch, height, pin count, and pad or ball layout? | Calibrated measurements plus exact outline drawing. | Footprint and assembly review. |
| Orderable package | Which manufacturer package code and full orderable number apply? | Product page, ordering table, marking lookup, label. | BOM release and substitution control. |
| Traceable identity | Do source and lot records support the claimed product? | Original label, chain of custody, lot/date data, inspection plan. | Risk-based incoming acceptance. |
Use a six-step package verification workflow.
Preserve the received state.
Before cleaning, desoldering, relabeling, or mixing units, photograph the top, bottom, all sides, carrier and complete label. Record supplier, PO, receiving lot and quantity.
Identify the manufacturer and complete MPN.
Capture every marking line and logo. Use the manufacturer’s lookup or datasheet to turn the abbreviated device code into a candidate, then recover the full orderable part number from the original label and purchase record.
Find the exact package designator.
Open the current manufacturer product page and ordering table. Separate package code from grade, finish, qualification and packing suffixes. Save the document revision used.
Compare the official mechanical outline.
Check terminal count, D/E body dimensions, overall lead span, maximum height, pitch, terminal width and length, exposed pad or ball map, and pin 1. Read each symbol from that drawing’s legend.
Measure and map the physical part.
Use an appropriate calibrated system, record uncertainty, and measure multiple units when accepting a lot. Start with the fastest eliminators: terminal count, body size, pitch, height, then underside geometry.
Reconcile and disposition.
Compare the physical result with the MPN, label, carrier, date/lot/trace data and PCB footprint. Release only when the evidence agrees; otherwise hold, document the conflict and escalate.
Start from the orderable code, then prove the geometry.
Retrieve the official ordering table and exact mechanical drawing before comparing the PCB footprint.
- Record full MPN and package drawing code.
- Confirm body, pitch, height, terminal map and pin 1.
- Keep the drawing revision with the BOM approval.
Read the top mark without mistaking it for the full part number.
Small packages often cannot carry the complete manufacturer part number. A top surface may contain an abbreviated device code, a grade character, date code, assembly-site data, trace code and pin-1 symbol. TI’s official marking lookup accepts either a marking or a TI part number and returns candidate products, package codes and pin counts. That makes it a strong starting point—not a substitute for the exact orderable code and outline.
| Observed element | What it may indicate | Why it can mislead | Verification action |
|---|---|---|---|
| Logo or maker name | Claimed original manufacturer. | May be omitted on tiny parts, revised, or imitated. | Compare with the family’s current marking guide. |
| Short device code | Product family, function or option. | A short code can be ambiguous outside manufacturer context. | Use the manufacturer’s reverse lookup or datasheet. |
| Suffix / grade character | Package, temperature, voltage, revision or finish. | Syntax is manufacturer- and family-specific. | Decode from the exact ordering table. |
| Date / lot / trace line | Production genealogy. | It can resemble the device code and may not be public. | Reconcile with the original label and trace record. |
| Dot, notch or chamfer | Often pin 1 or orientation. | A mold mark or defect may look like an indicator. | Use the exact package drawing and terminal map. |
A BOM that stores only the base device name can silently lose package, temperature, qualification, finish and shipping information. Keep the complete MPN plus a separate package description and drawing identifier.
Use the package drawing—not a distributor thumbnail.
Manufacturer package tools are designed for this task. TI lists package drawings with pin count, pitch, height, length and width. NXP’s package search links its SOT designators to mechanical outlines and JEDEC reference codes. Analog Devices’ package index filters by package type, drawing code, pin count, dimensions, outline and land pattern.
Confirm that the drawing applies to the exact package code and revision. A generic “QFN-32” image may omit body size, pitch, height, exposed-paddle geometry, terminal length, wettable-flank option or pin-1 convention. Also separate the component outline from the PCB land pattern: the footprint includes solder-joint, mask, paste and manufacturing allowances.
Measure in an eliminating order.
- Count terminals by side and total.
- Measure mold or substrate body length and width.
- Measure overall lead span separately.
- Measure pitch across several center-to-center intervals.
- Check height and standoff without compressing leads or balls.
- Map exposed pad, missing balls, segmented lands and pin 1.
Confirm pin 1 and the bottom-side pattern.
Two packages can share the same top-view body size and visible terminal count yet require different footprints. For QFN, DFN and LGA, map the perimeter lands, center paddle, corner shape, no-connect pads and any segmented geometry. For BGA and WLCSP, map rows, columns, pitch, populated and depopulated positions, and A1 orientation. Check whether the drawing is a top, bottom or transparent view before mirroring anything.
The center pad is not a counting shortcut.
An exposed paddle may be thermal, electrical, both, or divided into special zones. Marketing pin counts and drawing terminal conventions can handle it differently. Read the terminal table and notes for the exact device.
Analog Devices’ LFCSP guidance describes perimeter pads and an exposed paddle on the bottom surface; the paddle is soldered to the PCB for thermal performance. That assembly function is why a mismatched paddle is more than a cosmetic difference.
Watch these package-family traps.
SOIC / SOP / SSOP / TSSOP / MSOP
Gull-wing leads on two sides do not settle body width, lead span, pitch or height. “SOIC-8” can still hide narrow, wide and vendor-specific variants.
QFP / LQFP / TQFP / HTQFP
Four visible lead rows help identify the family, but the same pin count can appear in different body sizes, pitches, heights and exposed-pad options.
QFN / DFN / SON / LFCSP
Vendor terminology overlaps. Confirm whether terminals occupy two or four sides, then verify body size, pitch, paddle and side-wettable features.
LGA / custom leadless module
A flat bottom grid can include irregular ground, thermal or sensor pads. Do not force a perimeter-pad QFN assumption onto a custom land map.
BGA / FBGA / CSP-BGA
Body size and total ball count do not prove pitch or map. Depopulation and A1 orientation can change footprint compatibility.
WLCSP / WLP
The body is close to die size and device-specific bump maps are common. Backside marking, exact die outline and bump map matter.
A shipping suffix can change the carrier without changing the package.
The Analog Devices AD9253 ordering guide lists standard options such as AD9253BCPZ-105 and reel options such as AD9253BCPZRL7-105. Both are identified as a 48-lead LFCSP, 7 mm × 7 mm × 0.85 mm with exposed pad, using package option CP-48-13. The RL7 row adds a packing quantity of 750 on reel.
The exact orderable string matters commercially, but not every added suffix changes the molded package or PCB footprint. Verify package geometry from the package-option code and outline; verify carrier and quantity from the ordering/packing information. Do not strip the suffix from a purchase order, and do not infer body geometry from the reel code.
This is a documented manufacturer example from the AD9253 datasheet, not a YURUNOX shipment, test result, or customer case.
Illustrative buyer situations
The following composites show decision consequences. They are not claimed customer outcomes or first-hand YURUNOX experiences.
The quote says “QFN-32,” but the approved drawing says 4 × 4 mm.
The received unit is 5 × 5 mm with a different exposed paddle. The electrical base name appears similar.
Decision consequence: hold the lot. A matching family and pin count cannot overcome incompatible body and paddle geometry.
A supplier offers “SOIC-8 equivalent.”
The offered part has eight gull-wing leads, but body width and lead span correspond to a wide-body outline rather than the released narrow footprint.
Decision consequence: reject the shorthand comparison and request the exact MPN, package code and drawing before alternate review.
The top marking matches a candidate, but the label belongs to another suffix.
The device code is plausible, while carrier, lot data or bottom-side pattern does not reconcile.
Decision consequence: quarantine and investigate. A marking lookup returns candidates; it does not resolve conflicting receiving evidence.
Build an evidence packet that another reviewer can reproduce.
Identity record
Manufacturer, complete MPN, status, package family, proprietary code and drawing revision.
Mechanical record
Terminal count, body, height, pitch, lead span, exposed pad or ball-map identifier.
Orientation record
Pin-1 convention plus labeled top, bottom and side photographs.
Measurement record
Instrument, calibration, sample size, values, method and uncertainty.
Receiving record
Original carrier and labels, supplier, PO, quantity, lot boundary and chain-of-custody basis.
Engineering record
PCB footprint revision, land-pattern review, mismatch, concession and approval authority.
Use a stereo microscope for readable markings and lead condition. Use a calibrated vision system or optical comparator for fine pitch, and a suitable micrometer or caliper only where contact will not deform the package. A known-good sample can strengthen comparison when its identity and history are controlled.
X-ray, XRF, decapsulation, acoustic microscopy and electrical testing answer additional questions. They may be required by a counterfeit-control or failure-analysis plan, especially when hidden BGA construction, die attach, internal leadframe, material, or function is in doubt. They are not routine substitutes for the manufacturer drawing, and no single X-ray image proves authentic origin or complete electrical performance.
Put the package evidence in the RFQ—not after a mismatch.
Identify the exact requirement
- Manufacturer and full orderable MPN
- Approved package code and drawing revision
- Body size, pin/ball count, pitch and maximum height
- Exposed pad, wettable flank or ball-map requirement
- Temperature, qualification and finish
- Carrier, standard quantity and MSL handling
Define the evidence and disposition
- Source basis and traceability expectation
- Label plus top/bottom/side photographs
- Allowed date/lot policy and split-lot rules
- Dimensional sample plan and report fields
- Known-good comparison or additional tests, if required
- Quarantine and approval authority for any conflict
As an independent electronic-component sourcing partner, YURUNOX can align an offered part with the requested MPN, package option, quantity, carrier, available source evidence and customer-defined inspection requirements. Manufacturer package definitions and final engineering compatibility remain governed by the current manufacturer documentation and the customer’s approval process.
Connect the request to YURUNOX’s quality assurance process, purchasing experience, and global shipment workflow.
Need to verify a package before ordering?
Send the complete MPN, manufacturer, quantity, destination, label photos, top/bottom/side images, measured dimensions, PCB footprint, and the evidence required for approval.
IC package verification questions
Can I identify an IC package from the top marking alone?
Sometimes a manufacturer lookup returns a strong candidate, but confirm terminal count, body dimensions, pitch, orientation, underside geometry and the exact ordering option. Short codes can be ambiguous, and other lines may be date or trace data.
What is the fastest way to tell QFN from DFN?
A useful first clue is terminal placement: QFN-style packages commonly have perimeter terminals on four sides, while DFN-style packages commonly use two sides. Vendor names vary, so the bottom view, body, pitch, exposed pad and exact package code remain controlling.
How do I distinguish SOIC from TSSOP or SSOP?
Compare body width, height, lead pitch, lead span, pin count and exact outline. Family names alone are not enough because narrow, wide and vendor variants exist.
Does the package suffix always identify the package?
No. A suffix may also encode temperature, qualification, finish, reel, quantity or another option. Decode the complete orderable number using the exact manufacturer ordering table.
Should I measure the PCB footprint to identify the component?
Use it only as supporting evidence. A land pattern includes solder, mask, paste and manufacturing allowances, so it is not equal to component body or terminal geometry. Compare the component with its outline and the PCB with its recommended land pattern separately.
Why can the package pin count differ from what I count?
An exposed thermal pad, internally connected pads or no-connect terminals may be handled differently in descriptions and drawings. Use the terminal table and notes for the exact device rather than adding or subtracting the center pad by assumption.
Can two packages with the same body size and pin count need different footprints?
Yes. Pitch, terminal length, exposed-pad geometry, wettable flanks, pin-1 features and bottom-side maps can differ. Exact drawing codes and land patterns are required for interchangeability review.
Does a matching IC package prove the component is authentic?
No. It proves mechanical consistency with a claimed option. Authenticity decisions require traceability, source control and risk-appropriate inspection or testing.
Evidence used for this guide
- Texas Instruments Packaging Resources — official package, part-marking and carrier information entry points.
- TI Packaging Part Marking Lookup — marking-to-product candidates, package codes and pin counts.
- TI Find All Packages — package drawings, pin count, pitch, height, length and width.
- NXP Package Search — NXP package versions, descriptions, dimensions, outline drawings and reference codes.
- Analog Devices Package Index — outline drawings, package codes, dimensions, land patterns and material information.
- Analog Devices AD9253 Datasheet — documented ordering example for CP-48-13 and RL7 reel packing.
- Analog Devices AN-772 — LFCSP construction, exposed paddle and land-pattern guidance.
- JEDEC Registered Outlines: JEP95 — registered and standard package-outline resource index.
- TI Anti-counterfeit Guidance — source-control guidance and limits of appearance-based conclusions.
Checked August 28, 2026. Package drawings, markings, ordering codes and product status can change. Use the current manufacturer-controlled document for the exact part before approval.