Open-Drain vs Push-Pull Outputs: How to Choose

What is the difference between open-drain and push-pull?

In a basic CMOS open-drain stage, an NMOS transistor connects the output to ground when on. When off, the driver becomes high impedance. The pull-up then charges the wire and input capacitance. “Open” does not mean perfectly disconnected: leakage and protection structures still matter.

A CMOS push-pull stage adds an active path toward the supply. It can source current to raise the output and sink current to lower it. Neither state is an ideal voltage source: use the guaranteed high and low output voltages at the specified load, not an assumption that the pin reaches exactly VDD or zero.

Topology background: TI, Output Topology Options for a Voltage Supervisor.

How are open-collector and active-low different?

Open-collector uses a bipolar transistor rather than a MOSFET, but provides a similar sink-or-release function. Its leakage, saturation voltage and timing still need separate checks. Active-low describes the meaning of a signal: low means asserted. An active-low reset can be either open-drain or push-pull.

When can multiple outputs share one signal line?

Imagine two compatible fault outputs connected to one controller input and one pull-up. If either output pulls low, the controller sees a fault. The other output can release the wire without trying to force it high. Only when both outputs release can the pull-up establish high.

At the voltage-logic level, this is wired-AND: the line is high only when all participants release. Viewed as active-low fault events, it performs an OR: any asserted fault pulls the line low. A shared alarm tells you that a fault exists, not which device caused it; read individual status registers or use separate inputs when identification matters.

Each device must be able to sink the entire pull-up current when it alone asserts. Do not divide that current by the number of outputs on the wire.

Why is the same connection risky with push-pull?

If one enabled push-pull output drives high while another drives low, current flows from one driver through the other. Matching normal firmware states does not prevent disagreement during reset or startup. A deliberately designed tri-state bus is different: it needs explicit output-enable ownership and safe turnaround timing.

Why does I2C use this topology?

Standard-mode and Fast-mode I2C use open-drain/open-collector signaling so devices can release or pull the bus low. Do not substitute a push-pull GPIO setting simply to make the rising edge look sharper.

The mode matters: Ultra Fast-mode uses a different, unidirectional push-pull arrangement. See NXP UM10204, sections 3.1 and 3.2.

How do you calculate an open-drain pull-up resistor?

A pull-up has two competing jobs: raise the line quickly enough, but allow the weakest output to pull it low. Calculate both bounds before choosing a standard resistor value.

IOL is the current at which the datasheet guarantees your chosen VOL(max), at the relevant supply and temperature. It is not an absolute-maximum pin current. Calculate the low-level bound for each potential sinking device and use the most restrictive result. Extra load current requires a separate current budget.

The upper bound models a passive pull-up charging a lumped capacitance. The factor 0.8473 applies to a 30%–70% rise time; a 10%–90% RC rise is approximately 2.2RC. Do not mix measurement conventions or apply this simple model unchanged to active pull-ups and buffered bus segments. Equations: TI SLVA689.

For conventional I2C, the maximum 30%–70% rise time is 1,000 ns in Standard-mode and 300 ns in Fast-mode. Those are rise-time limits, not complete clock periods; other timing conditions must also pass. NXP UM10204, Table 11.

What if the minimum is greater than the maximum?

Change only the example's capacitance to 400 pF: the upper bound falls to about 885 Ω, below the 1.02 kΩ lower bound. There is no passive resistor value that meets both assumptions. Reduce capacitance, select a supported slower mode, or assess an appropriate bus buffer or stronger specified driver. A smaller resistor alone trades a timing problem for a low-level-current problem.

How do parallel pull-ups change the result?

A schematic may show one 4.7 kΩ pull-up while attached modules each add another. All resistors connected to the same net and same rail contribute to the effective pull-up.

What must you check across voltage domains and power states?

Open-drain can help connect voltage domains, but only if every attached pin tolerates the pull-up voltage and every receiver recognizes the resulting levels. A 3.3 V output label does not, by itself, authorize a 5 V pull-up.

What high level does the receiver require?

For a hypothetical 5 V receiver requiring VIH ≥ 0.7 × VDD, high must reach at least 3.5 V. A 3.3 V pull-up cannot guarantee that. Raising the pull-up to 5 V may then violate another device's pin rating. The solution may require a suitable level translator, not a different resistor.

Leakage can also lower the released voltage. In a simplified example, 50 µA flowing away from the node through a 10 kΩ pull-up causes a 0.5 V drop. Sum worst-case leakage at the relevant temperature and use the minimum pull-up supply when checking high-level margin. Check VOL against the receiver's VIL limit as well.

Can a live pull-up feed an unpowered rail?

If a connected pin has a protection path to its supply, an external high level can inject current when that supply is off. Possible consequences include a clamped bus, excessive leakage or a partially powered device. Setting an output to “released” in firmware does not remove the pin's physical protection structures. TI's powered-off protection discussion illustrates this failure mechanism.

Review at least three states: all supplies on; the pull-up rail on while a connected IC is off; and a driver powered while the pull-up rail is off. Then examine supply ramps, reset and sleep transitions. ST's AN4899, section 6.3 specifically cautions against treating powered five-volt tolerance as protection when the MCU is unpowered.

How do rise time, PWM duty cycle and power affect the choice?

Push-pull commonly gives faster rising edges into the same capacitive load because it actively sources charging current. That is not a universal speed ranking: compare actual load, drive strength, slew controls, propagation delay and timing specifications.

With open-drain PWM, the pull-up's slow rising edge may cross the receiving threshold later than expected. The receiver can therefore see a shorter high pulse even when an instrument reports the correct repetition frequency. Falling-edge delay matters too; there is no universal duty-cycle correction factor.

Slow transitions can also increase current or create false switching at ordinary CMOS inputs. Verify the receiver's input transition requirement. A suitable Schmitt-trigger input can improve noise immunity, but it does not make a late edge meet the interface timing budget. See TI, Implications of Slow or Floating CMOS Inputs.

How much power does the pull-up use while the line is low?

For an illustrative nominal 3.3 V rail and 2.2 kΩ pull-up, taking VOL as approximately zero gives 1.5 mA and 4.95 mW in the resistor while low. If low occupies 20% of the time, that resistor's average contribution is about 0.99 mW. This excludes switching energy, leakage and IC supply consumption.

Push-pull avoids that particular continuous pull-up loss in a low state, but still uses energy to charge capacitance and switch. For battery designs, include how long a fault or interrupt remains asserted, not just how often it changes.

Which datasheet details can change a replacement decision?

How should you troubleshoot an output that fails?

Start with the schematic, complete part numbers and actual GPIO configuration. On configurable MCUs, output type, pull-up enable, alternate function and speed settings are distinct decisions. ST's GPIO application note illustrates these controls; use it together with the exact device's reference manual.

A probe adds capacitance. Use suitable probing and grounding, include the loading in your interpretation, and check worst-case supply, temperature and connected-module conditions. One good room-temperature waveform is not a complete qualification.

Which output type should you choose, and what must purchasing verify?

1. Define who owns the wire.

   One active source usually points toward push-pull. Several compatible sources asserting the same low event point toward open-drain. Follow the protocol when it mandates a topology.

2. Write down the complete electrical conditions.

   List supply rails, permitted pin voltages, receiver thresholds, guaranteed drive levels, total capacitance, timing and all powered-off states.

3. Include the supporting circuit.

   Record pull-up value and tolerance, optional module pull-ups, input leakage, startup bias, output-enable behavior and firmware mode. Reset and power-good signals also need valid-output and delay specifications.

4. Approve the complete ordering code.

   Match topology, polarity, package and pinout as well as temperature grade, qualification needs and lifecycle. Availability and a similar part number are not evidence of electrical interchangeability.

For an RFQ, send the full manufacturer part number, package, quantity and required delivery date. For an alternative review, add a short interface brief: “shared active-low fault, 3.3 V pull-up, 100 pF maximum, specified VOL/IOL, powered-off pin tolerance required.” Treat those values as requirements to verify, not as an automatic compatibility approval.

Keep sourcing and engineering checks separate. Review YURUNOX's purchasing process and quality assurance information for order-related requirements, while the design owner confirms interface suitability from the manufacturer documentation.