QFN vs QFP vs BGA vs LGA: How to Select the Right IC Package
There is no universal best IC package. Choose QFP when visible gull-wing leads and accessible rework matter; QFN when a compact leadless body and a controlled exposed-pad design fit the board; BGA when high I/O density justifies area-array routing and hidden-joint controls; and LGA only after confirming the exact soldered or socketed interface.
The package acronym is only the start. Engineering, manufacturing, and purchasing still need the complete manufacturer part number, package drawing, pin or ball map, grade, moisture status, packing method, and approved assembly route.
Which Package Fits Your Design: QFN, QFP, BGA, or LGA?
Start with the limiting requirement, not a generic package ranking. A QFP can be the practical choice for visible joints and service access. A QFN can save board area and create a direct die-to-board thermal path when its exposed pad is designed and soldered correctly. A BGA can support the terminal count and routing topology that perimeter packages cannot. An LGA must be evaluated from its exact construction and attachment system.
No family-level description approves a device. The exact data sheet, package drawing, land-pattern guidance, board stack-up, factory capability, and program qualification remain controlling.
| Decision factor | QFP | QFN | BGA | LGA |
|---|---|---|---|---|
| Terminal interface | Gull-wing leads on four sides. | Leadless bottom terminations, often with a central exposed pad. | Solder balls distributed under the package. | Flat lands under the package; the part may be soldered or socketed. |
| Where it often helps | Visible solder-joint access, probing, and lead-level service. | Compact area for moderate I/O and a short thermal path into the PCB. | High terminal count and dense interconnect in an area array. | Dense land arrays or a specific matched socket/contact architecture. |
| Board impact | Perimeter escape; fine pitch still challenges trace and spacing rules. | Perimeter escape plus exposed-pad copper, paste segmentation, and thermal vias. | Inner-ball escape may require via-in-pad, added layers, or HDI capability. | Depends on land map, pitch, depopulation, and soldered versus socketed use. |
| Inspection reality | Many lead and fillet features remain optically accessible. | Bottom joints and the exposed pad are hidden or only partly visible. | Reflowed ball joints are hidden under the body. | Soldered joints are hidden; socketed systems add contact and loading checks. |
| Common quote trap | Different pitch, body, finish, grade, or packing behind a similar base number. | Unresolved package code, exposed-pad requirement, MSL, or reel suffix. | Ball map, pitch, alloy, MSL, tray/reel protection, or rework route omitted. | “LGA” quoted without the exact attachment route or matched socket system. |
Scroll the table on small screens. These are comparison directions, not guaranteed values for every QFN, QFP, BGA, or LGA.
What Does Each Terminal Interface Require From the PCB?
The useful visual question is not which black body looks smaller. It is where the electrical and mechanical joints sit, which features remain accessible after assembly, and what the PCB or socket must provide.
Why Does “LGA” Not Automatically Mean Socketed?
NXP describes an LGA as a molded area-array package that can be used in a socket or connected to a board with solder paste. The flat lands distinguish it from a BGA with attached spheres, but the acronym alone does not define stencil, standoff, contact force, reflow, inspection, or field replacement.
Intel’s processor guide illustrates one socketed implementation: an FC-LGA processor must match a specific socket, motherboard, and BIOS support. Therefore a land count such as “LGA1700” is still not a complete component or compatibility specification.
Read NXP’s LGA assembly guidance →How Do Assembly, Inspection, and Rework Requirements Differ?
Visibility changes the control plan; it does not remove the need for one. QFP exposes many external lead features to optical inspection. QFN, BGA, and soldered LGA move important joints under the body. Hidden does not mean defective, and an X-ray image does not by itself mean accepted.
| Process stage | QFP | QFN | BGA | Soldered LGA |
|---|---|---|---|---|
| Paste and placement | Lead pitch, coplanarity, pad geometry, orientation, and toe/heel alignment. | Perimeter paste plus exposed-pad aperture segmentation and via strategy. | Ball map, pad definition, warpage, placement, and supported board escape. | Land map, paste volume, coplanarity, standoff, and package-specific guidance. |
| Reflow and moisture | Use the exact package peak limit and measured board profile. | Control MSL/floor life, exposed-pad solder volume, and measured joint profile. | Protect balls and dry pack; control board support, warpage, and measured profile. | Follow the device-specific MSL, paste, profile, and handling requirements. |
| Post-reflow evidence | AOI can assess many gull-wing joint features; electrical test still matters. | Process qualification, X-ray, electrical test, or other evidence may be needed for hidden areas. | X-ray can support monitoring for bridges, opens, and voids when the method and criteria are defined. | Evidence depends on land access, pitch, application risk, and the approved process. |
| Rework | Leads are accessible, but fine pitch and nearby parts can still make rework difficult. | Requires controlled heat, pad protection, paste volume, alignment, and hidden-joint verification. | Requires controlled removal, site preparation, alignment, board support, profile, and inspection. | Requires the manufacturer’s attachment-specific route; socket service is a different process. |
Inspection scope must name the defect mechanism, equipment/view, sample logic, acceptance source, and disposition owner. “AOI included” or “X-ray passed” is not a complete requirement.
What Can the TI QFN Result Actually Prove?
TI’s 56-pin RGQ report compares an 8 × 8 mm QFN footprint of 64 mm² with a listed 12 × 12 mm, 64-pin TQFP footprint of 144 mm². Its thermal discussion assumes the exposed pad is soldered and warns that system performance depends on board construction, airflow, spacing, and orientation.
This supports a mechanism and a defined test result. It does not promise the same footprint advantage, thermal performance, yield, or life for a different device, board, solder system, or mission profile.
Review TI application report SCEA032 →Why Did NASA/JPL Use More Than One Inspection Method?
A NASA/JPL program evaluated high-I/O CGA, LGA, and BGA assemblies on HDI boards. It reported up to 500 thermal cycles and used optical photomicrographs, real-time 2D X-ray, dye-and-pry, cross-section, and scanning-electron-microscopy evidence.
The test vehicle, package construction, PCB microvia system, reflow route, thermal profile, and failure-analysis method were all part of the evidence. That makes the lesson operational: area-array qualification is a board-and-process exercise, not a package-name endorsement.
Review NASA NTRS record 20160001775 →
Which Package Should You Investigate for Space, I/O, Visibility, or Socketing?
Use the limiting requirement to choose the first package direction, then test that direction against the exact device and production system. This is a screening aid, not an approval.
Investigate QFN for moderate I/O and BGA when terminal count or signal topology requires an area array.
- Compare breakout area, not body area alone.
- Include QFN exposed-pad copper and via space.
- Price BGA routing layers, HDI, inspection, and rework.
- Verify the compact package is available in the approved grade.
Investigate QFP when lead visibility, probing, and lead-level service matter. Fine pitch, board density, exposed pads, and lead damage can still make it difficult.
- Check that I/O count fits a practical body and pitch.
- Protect lead coplanarity through packing and handling.
- Define AOI and test access.
- Plan service-life supply before freezing the footprint.
Investigate BGA when a perimeter package cannot support the terminal count, power distribution, or signal escape.
- Control pitch, ball map, depopulation, and via rules.
- Confirm the board supplier can build the escape strategy.
- Qualify profile, warpage, evidence, and test coverage.
- Establish a rework and spare-part route.
Investigate the exact socketed LGA device and matched contact system—not LGA as a generic family.
- Confirm that the exact MPN is intended for socket use.
- Match socket part number, revision, keying, and land map.
- Verify board, loading, retention, and thermal hardware.
- Check platform and firmware support where applicable.
When Is a Different Package a Redesign Rather Than a Drop-In Substitute?
Treat a QFP-to-QFN, QFN-to-BGA, BGA-to-LGA, or other package change as a proposed alternate until the complete device, board, factory, test, and customer impacts are approved. Similar silicon function does not make the packages interchangeable.
| Impact area | What must be compared | Evidence required before approval | Hold condition |
|---|---|---|---|
| Electrical identity | Full MPN, pinout/ball map, voltage, speed, temperature grade, qualification, programming state, and errata. | Exact data sheets, ordering tables, comparison record, and engineering approval. | Any changed electrical or grade field remains unexplained. |
| PCB and mechanics | Footprint, pitch, escape routing, stack-up, exposed pad, thermal vias, height, keep-outs, and test access. | Controlled footprint/drawing, layout review, DFM feedback, and mechanical/thermal analysis. | The PCB or socket cannot be tied to the offered package. |
| Assembly and quality | Stencil, placement, reflow, MSL handling, inspection, electrical test, rework, and reliability environment. | EMS process review, qualification plan, build evidence, and acceptance criteria. | The factory has no approved process or evidence route. |
| Supply and lifecycle | Availability, packing, standard pack, lot/date policy, approved sources, spare strategy, and change notices. | Supplier quotation, lifecycle evidence, traceability terms, and controlled alternate status. | The commercial offer silently changes package, grade, condition, or evidence. |
Compare the full MPN, pinout, electrical limits, qualification, package drawing, thermal data, firmware/configuration, and lifecycle.
Include a new footprint, exposed-pad copper and vias, prototypes, thermal validation, stencil work, and updated test access.
Ask the EMS for profile development and hidden-joint evidence. Field repair may shift from lead-level work to package removal and replacement.
If area reduction enables the product, QFN may justify the change. If service and existing-tool reuse dominate, QFP may carry lower total risk.
What Should Engineering, the EMS, and Procurement Approve Before Release?
The decision is complete only when the orderable device, board, production process, inspection route, and purchase record agree. Each owner should produce evidence the next owner can inspect.
- Complete MPN, grade, pinout, package drawing, and land-pattern source
- Escape routing, stack-up, exposed-pad design, test access, and clearances
- Thermal model, mechanical environment, qualification, and alternate record
- Stencil, paste, placement, profile, MSL/floor-life, and handling controls
- AOI, X-ray, electrical-test, sampling, defect, and acceptance definitions
- Rework equipment, board support, site preparation, and verification route
- Exact suffix, packing code, reel/tray/tube, standard pack, and quantity
- Condition, date/lot policy, original labels, MSL/dry pack, and traceability
- Physical stock, delivery commitment, exception disclosure, and claim route
- Freeze the exact device and package requirement.
Record the complete manufacturer code, controlled drawing, grade, quantity, destination, and required delivery state. Keep every alternate on a separate line.
Output: approved BOM identity and package basis. - Confirm the board and production route.
Obtain PCB-fabricator and EMS feedback on routing, stencil, placement, reflow, moisture controls, inspection, test, and rework.
Output: DFM and manufacturing acceptance tied to the exact package. - Define evidence and stop conditions before the PO.
Name the required pack/label records, inspection or test evidence, sample-plan source, mismatch response, and release owner.
Output: measurable acceptance requirements and exception route. - Receive against the same controlled record.
Preserve pack-to-lot identity, compare labels and parts, inspect package-specific risks, and hold any mismatch before repacking or issue.
Output: documented accept, hold, or reject disposition.
What Evidence Should Buyers Put in a QFN, QFP, BGA, or LGA RFQ?
A strong RFQ prevents a supplier’s shorthand description from becoming an unauthorized package substitution. Ask the supplier to list every package, grade, packing, condition, or documentation exception separately.
| RFQ field | State or request | Why it matters |
|---|---|---|
| Identity | Manufacturer, complete MPN/suffix, package code/drawing, body size, terminal count, pitch, and pin/ball/land map. | A family name or acronym can hide a different footprint, pinout, grade, finish, or pack. |
| Electrical and qualification | Voltage/speed option, temperature grade, applicable qualification, lead finish, programming state, and approved BOM revision. | The same body does not prove the same electrical or qualification status. |
| Package-specific requirement | QFP lead condition; QFN exposed pad; BGA ball map/alloy when controlled; LGA soldered or socketed plus the matched interface. | Mechanical acceptance and assembly route differ with terminal geometry. |
| Lot, label, and packing | Condition, date/lot policy, original manufacturer labels, lot-mixing rule, reel/tray/tube, quantity per pack, MSL/dry pack, and storage evidence when required. | Protection and moisture status affect receiving and reflow readiness. |
| Inspection and test | Pre-shipment photos, incoming scope, anomaly criteria, justified X-ray/electrical test, report format, sample-plan source, and hold/release authority. | “Inspection included” is not a measurable acceptance requirement. |
| Commercial controls | Quantity, target date, destination, currency, Incoterm/named place, stock commitment, quote validity, NCNR/cancellation, warranty, claim route, and return condition. | A correct part can still create supply or claim exposure if terms are unclear. |
Supplier request to adapt for the program
Please quote the exact manufacturer MPN and package suffix only. Confirm the manufacturer, package code and drawing, body size, terminal count, pitch, and pin, ball, or land-map reference; electrical, temperature, and qualification grade; condition, date-code and lot policy; reel, tray, or tube format and original labels; MSL and dry-pack information; source and traceability evidence; physical stock and committed ship date; and the agreed inspection or test evidence. For LGA, state whether the exact device is soldered or socketed and identify the matched socket/contact system when applicable. List every package, grade, packing, condition, or documentation exception on a separate line. Do not substitute a QFN, QFP, BGA, or LGA variant without written engineering approval.
What Should Incoming Inspection Check Before Material Release?
First match the PO, outer label, inner pack, complete MPN, suffix, quantity, and approved revision. Preserve original packaging, lot segregation, and moisture status. Appearance can identify anomalies; it cannot by itself prove authenticity, electrical suitability, or a safe assembly process.
Check marking, body damage, cracks, bent or contaminated leads, pack protection, and controlled coplanarity concerns. Do not straighten leads outside an approved process.
Check identity, visible terminal-side features, body condition, orientation, reel/tray label, MSL label, dry pack, and any exposed-pad evidence defined by the plan.
Check identity, tray/reel protection, accessible array condition under the controlled method, ball protection, dry pack, MSL label, and lot segregation.
Check land/contact condition and the documented soldered or socketed route. For socketed systems, keep the exact socket and platform requirement tied to the part record.
Identity, condition, pack records, and required evidence match the PO and approved acceptance plan.
A difference may be reconcilable, but the affected quantity stays segregated until evidence and the authorized owner resolve it.
A confirmed mismatch or failure meets the agreed rejection criteria and follows the documented claim or return route.
Primary technical references and image licenses
Technical sources were rechecked on September 6, 2026. Manufacturer notes are package- or family-specific; use the current exact-device data sheet, drawing, packing record, and applicable program requirements before approval.
- Texas Instruments, 56-Pin Quad Flatpack No-Lead Logic Package (SCEA032) — package comparison, thermal-model limits, board-level test conditions, assembly, and packing.
- Texas Instruments, QFN and SON PCB Attachment, Rev. C — land pattern, stencil, reflow, inspection, and rework guidance.
- Texas Instruments, AN-1126 BGA (Ball Grid Array), Rev. C — BGA assembly, X-ray monitoring, and rework context.
- NXP, Assembly Guidelines for Land Grid Array Package — soldered/socketed LGA construction and process guidance.
- Microchip AN2089, Package Application Note for QFN and DFN Packages — handling, land pattern, assembly, and rework scope.
- Infineon, Recommendations for Board Assembly of Quad Flat Packages, Rev. 6.0 — QFP geometry, AOI, reflow, and rework.
- NASA/JPL, Reliability of CGA/LGA/HDI Package Board/Assembly — public test program, inspection methods, thermal cycling, and failure analysis.
- Intel, Package Type Guide for Desktop Processors — FC-LGA/socket architecture and compatibility limits.
- Licensed visuals: package comparison, QFP, QFN, BGA diagram, LGA, BGA cross-section, and pad cratering. License and creator details appear in the corresponding captions.
YURUNOX is an independent electronic-component distributor and sourcing partner. The cited manufacturers and product names belong to their respective owners; references do not imply manufacturer endorsement of YURUNOX or approval of a specific purchase.
Need a quote tied to the exact approved package?
Share the complete manufacturer part number and the package evidence your team needs. YURUNOX can help organize the sourcing request, offered configuration, packing, traceability, and disclosed exceptions for your engineering and quality review.
- Complete MPN, suffix, grade, and quantity
- Package drawing or approved footprint reference
- Reel, tray, or tube and MSL/dry-pack needs
- Date/lot, traceability, and inspection requirements
- Written approval rule for every alternate
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