What Is a Digital Isolator? How It Works
A digital isolator transfers logic information between circuits without a direct conductive signal connection. It encodes the input, sends that information across an insulating barrier using electric or magnetic fields, and rebuilds the output relative to the receiving circuit's ground.
The key distinction: it transfers the meaning of a high or low, not the original wire, ground reference or supply power. Choosing one requires a signal plan, a power plan and the right insulation specifications.
What does a digital isolator actually change?
It lets each circuit interpret logic relative to its own local ground. This is useful when ground potentials differ or a designed insulation barrier must separate two parts of the equipment. The barrier is only effective at system level if other connections do not bypass it.
Data is regenerated.
The receiver produces a new logic output, with some delay.
Power is a separate requirement.
A signal-only part normally needs a supply in both domains.
Three ratings, three questions.
Working voltage, withstand voltage and CMTI are not interchangeable.
The suffix matters.
Channel direction, startup defaults and package can change the result.
| Your requirement | Start with | Evidence to verify | Stop if |
|---|---|---|---|
| Transfer logic between separate electrical domains | A signal isolator with a defined channel map | Both local supplies, grounds, direction, timing and system connections | A cable, instrument, shield or return wire bypasses the barrier |
| Transfer logic and power a remote circuit | A signal isolator plus isolated DC/DC, or an integrated isolated-power part | Remote load, startup current, conversion limits, heat and external components | The selected part cannot supply the remote load under actual conditions |
| Isolate I²C, CAN, RS-485 or a gate-control function | A bus-specific isolator/transceiver or isolated gate driver | Open-drain behavior, transceiver functions, gate current and protection | A generic channel count is being used to claim interface equivalence |
| Meet a high-voltage or fast-switching requirement | Working-voltage, transient, creepage/clearance and CMTI review | Waveform, polarity, test method, package certificate and board geometry | A temporary withstand or headline data-rate value is treated as the design limit |
Imagine a controller reading a sensor board whose ground moves relative to the controller ground. A direct logic connection asks the receiver to judge a voltage against a reference that may no longer match the transmitter's. Isolation transfers the information without requiring that direct reference connection.
Here, “ground” means the local circuit reference; it does not necessarily mean protective earth. A programmer, shared supply return or grounded test instrument can create a conductive route around the barrier. Review the complete connected system, not just the isolator symbol. TI's Digital Isolator Design Guide explains this two-domain architecture.
Not an analog isolator or a universal noise filter. A logic isolator reconstructs high and low states, not an arbitrary analog waveform. A false edge already accepted at its input may still be transmitted. Analog measurements require a suitable isolation amplifier or conversion to digital data before isolation.
How does a digital isolator work?
The process is recognize, encode, couple and reconstruct. First, the input circuit recognizes a logic level. A transmitter converts that state into a changing internal signal. Electric or magnetic coupling carries the information through insulation. A powered receiver then recreates the output logic.
Capacitive isolation uses an electric field
An insulating layer separates conductive structures. The changing electric field couples an encoded signal across that structure without a continuous metal path between domains. TI's ISO774x family, for example, uses a silicon-dioxide barrier and on-off keying, or OOK: a carrier represents one state; its absence represents the other. The carrier is internal, not the application's data clock. See the ISO774x datasheet, Section 7.
Magnetic isolation uses tiny transformer structures
Current changes in a transmitting coil create a magnetic field; the receiving coil detects the resulting signal while remaining electrically separate. Encoding varies. Some designs use short pulse patterns to describe rising and falling input edges. A transformer-based part is not defined by one universal internal protocol. Analog Devices explains the coupling and encoding principles.
How does an unchanged high or low get through?
The circuit communicates the state, not DC current through the insulation. Edge-based implementations may send refresh updates when the input has not changed. The ADuM1100 datasheet describes pulse-transformer transmission, periodic updates and a watchdog. In OOK implementations, carrier detection conveys the state. Neither mechanism means an unpowered receiver can actively drive a valid output.
Digital isolator vs optocoupler: what changes?
Both can isolate information, but an optocoupler sends it using light. In ordinary component terminology, a digital isolator usually means a non-optical device using capacitive or magnetic coupling. Similar purpose does not make the parts interchangeable.
Compare the input circuit first
A common transistor-output optocoupler needs LED current and an output circuit sized around its current transfer ratio, or CTR. A typical logic-input digital isolator instead needs a powered logic input referenced to its local ground.
Replacing one with the other can therefore change resistors, supplies, logic polarity and startup behavior before speed or package size even enters the discussion.
| Design question | Non-optical digital isolator | Optocoupler |
|---|---|---|
| What crosses the barrier? | Encoded electric or magnetic signal | Light from an emitter |
| What drives the input? | Usually a logic voltage and local supply | Usually LED current; device dependent |
| What affects timing? | Delay, distortion, skew and minimum pulse width | Emitter/receiver response and circuit loading |
| What must age gracefully? | Semiconductor circuitry and insulation | Those requirements plus light-output degradation |
| Is it a drop-in replacement? | Only after checking the full pinout, drive circuit, supplies, defaults, timing and insulation documentation | |
CTR is relevant to transistor-output optocouplers; high-speed logic optocouplers need their own comparison. See TI's discussion of input drive, timing and LED aging. There is no universal rule that every digital isolator is faster, cheaper or lower-power than every optical part.
For a purchasing decision, ask what the replacement improves and what must be requalified. A proven optocoupler circuit may be worth retaining when the proposed change adds engineering work without solving a real problem.
How Do Signal Isolation and Isolated Power Work Together?
A conventional signal-only isolator needs energy in both domains. The receiving-side supply powers its detector and output buffer; the signal barrier does not power the whole remote circuit. An independent local supply or an isolated DC/DC converter can provide that energy.
What if the isolator includes a DC/DC converter?
That is an additional function, not a property of every digital isolator. TI's ISOW774x family integrates isolated power conversion. You still need to budget remote startup and operating current, conversion losses, temperature and external components. The available load capability depends on the selected operating conditions.
Practical purchasing question: is the requirement “isolate these four logic signals” or “isolate these signals and power the remote ADC”? Those can lead to different parts, layouts and qualification work.
Which Interface and Channel Directions Does the Design Require?
Count directions, not just pins. An ordinary logic isolator does not automatically implement bidirectional I²C, a differential field bus or a power transistor's gate-drive stage.
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GPIO, UART and SPI: map every direction
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Directional logic channels can serve GPIO and UART signals. A conventional four-wire SPI link commonly needs three channels toward the peripheral and one return channel. Add interrupts, reset or extra chip-select signals to the map. For shared MISO wiring, verify whether the isolated output can become high impedance when deselected; an always-driven output can cause contention.
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I²C: open-drain and bidirectional behavior matter
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I²C uses pull-ups and devices that pull a line low. Ordinary push-pull channels cannot simply be connected in both directions without considering feedback and bus contention. TI's ISO1640 has bidirectional SDA and SCL paths; ISO1641 has bidirectional SDA but unidirectional SCL. If the peripheral must stretch the clock, that difference matters. Also check low-level thresholds, capacitance and pull-up requirements on each side.
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CAN and RS-485: isolation is not the transceiver
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A logic isolator does not create CANH/CANL or the RS-485 differential bus. Use a suitable transceiver plus isolation, or an integrated isolated transceiver. The ISO1042, for example, includes the CAN physical interface and isolation. Termination, protection, network timing and the bus-side supply remain separate design checks.
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MOSFET or IGBT control: include the gate driver
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Carrying a PWM command is not the same as charging and discharging a power transistor's gate. An isolated gate driver adds a suitable output stage and specified control functions. The UCC21520 family illustrates this category, with undervoltage lockout, disable and dead-time functions. Choose the actual gate-drive voltage, current and protection behavior required by the transistor and circuit.
Category mismatch cannot be fixed by a higher kV number. Confirm what the component must do electrically before comparing its insulation rating.
How Should Buyers Read Digital-Isolator Isolation Ratings?
The largest kilovolt number on a product page is not a continuous-use voltage. Record the normal voltage across the barrier, its waveform, repeated peaks and expected transient conditions before comparing parts.
| Specification | What it describes | What to verify |
|---|---|---|
| Working voltage | Long-term stress across the insulation | RMS/DC definition, waveform and lifetime conditions |
| Repetitive peak voltage | Repeated peak stress | Allowed peak and applicable waveform |
| Withstand voltage | A defined temporary voltage test | Test duration and certification basis |
| Surge voltage | Specified impulse withstand capability | Waveform, polarity and test conditions |
| Creepage | Shortest relevant path along an insulating surface | Package and assembled-board geometry |
| Clearance | Shortest relevant path through air | Package, board and equipment requirements |
Definitions and test context: TI, High-voltage reinforced isolation. Required values are application dependent; there is no universal spacing rule for every isolated board.
Basic and reinforced are not just voltage tiers
Functional isolation can support circuit operation without providing shock protection. Basic insulation provides a basic level of protection against electric shock; reinforced insulation provides protection equivalent to double insulation under applicable requirements. These terms describe protection arrangements, not simply “low, medium and high kV.”
Safety boundary: a hypothetical “5 kV withstand” label does not permit continuous 5 kV operation. Hazardous-voltage equipment needs qualified engineering and compliance review of the complete insulation system, exact device/package certificates, environment and board layout. A component certificate does not certify the finished product.
What is CMTI, and why is it not data rate?
Common-mode transient immunity (CMTI) describes correct operation while the voltage difference between the two grounds changes rapidly. It is commonly specified in kV/µs. Data rate describes information transfer; CMTI describes tolerance to a disturbance. A slowly changing enable signal can still cross a barrier exposed to a fast power-stage transition.
For an illustrative 400 V change in 20 ns, the average slew rate is 20 kV/µs. The equality is convenient: 1 V/ns = 1 kV/µs. Real edges can have ringing or steeper local slopes, so an endpoint average is not a worst-case immunity requirement. TI's CMTI application article explains the disturbance mechanism.
Why Doesn’t a High Mbps Rating Guarantee a Fast SPI Link?
Propagation delay shifts an edge in time. Pulse-width distortion changes the duration of a pulse. Channel-to-channel skew changes the relative arrival times of related signals. Those effects answer different questions from the maximum data-rate headline.
The return data arrives after the sample edge
Consider a controller that samples returned SPI data half a cycle after the launch edge. Its clock first crosses the isolation barrier, the peripheral produces data, and that data crosses back. Assume 12 ns outbound delay, 10 ns peripheral clock-to-output delay, 12 ns return delay and 6 ns for setup, board delay and uncertainty.
Corresponding clock ceiling = 1 / (2 × 40 ns) = 12.5 MHz
In this simplified example, 10 MHz provides a 50 ns half-cycle; 20 MHz provides only 25 ns. The latter misses the 40 ns budget even if the isolator's advertised one-way data rate looks ample. A production design still needs appropriate margin, guaranteed delay limits and verification of its actual SPI mode.
Analog Devices' AN-1478 documents this round-trip issue and alternatives such as delayed clock or delayed readback. The lesson is to calculate the complete launch-to-sample path; the example above is not a universal SPI limit or a recommendation to run at the calculated ceiling.
What Startup and Power-Loss Behavior Must a Substitute Match?
A normal truth table is not enough. An undriven input, missing transmitting supply, missing receiving supply and disabled output are different conditions. Check each one against the receiving circuit's required state.
In the ISO774x family, the F suffix selects default-low behavior; corresponding non-F versions default high under the documented conditions. The receiver still needs valid power, and enable settings matter. “Default low” does not mean an unpowered output actively holds a line low. Review the functional-mode tables.
The footprint matches, but the enable behavior changes
A hypothetical controller holds a downstream subsystem disabled until communication starts. Procurement receives an alternate with the same package and channel directions, but a different default-output variant. If the receiving rail starts first, the subsystem could see an unintended enable level.
Approval step: compare full orderable numbers, default and enable tables, unpowered-pin behavior and the intended supply sequence. The engineering response might be the correct variant, suitable external biasing or an independent interlock. A low default is not automatically the right choice if the downstream enable is active low.
Record the decision: retain the approved functional comparison with the BOM. “Pin compatible” and “traceable supply” address different questions; neither proves electrical or safety equivalence.
Why can an isolated circuit still have noise problems?
Insulation does not eliminate parasitic capacitance. Fast voltage changes can drive high-frequency displacement current through the component, the power converter and the board. Local rail noise, a poor return path or an unintended external ground connection can also undermine the intended result.
Review every path across the boundary
Trace supplies, shields, connectors, mounting hardware, test leads and intentionally fitted coupling components. Distinguish a direct conductive bypass from capacitive coupling that may be intentional and must be assessed for the equipment.
A photograph can reveal useful questions, but it cannot establish the circuit's net connections, insulation capability or certificate status.
ISOW7741: integrated power does not remove EMC work
TI's application brief SLLA561 explains emissions from an ISOW7741 implementation. It traces common-mode and differential-mode current loops and shows a layout approach using local decoupling, ferrite beads and defined keep-out zones. The note also stresses that test cables and earth connections should represent the intended system.
What this changes in a design review: budget space and components for the manufacturer's power and layout guidance before treating an integrated-power isolator as a board-area saving. Copying one headline isolation rating cannot replace that work. This is a published TI example, not a YURUNOX test; its specific layout does not guarantee compliance in another assembly.
| Observed symptom | Possible explanation | Next check |
|---|---|---|
| Works slowly, fails at speed | Timing or pulse-width limitation | Launch-to-sample path, loading and guaranteed delays |
| Unexpected startup state | Default variant, enable or supply sequencing | Both supply ramps and functional-mode tables |
| Errors during power switching | Common-mode disturbance or local rail noise | CMTI conditions, decoupling and coupling paths |
| Ground separation is lost | Another conductive connection | Supplies, cables, shields and instrumentation |
Measure safely. Use equipment and probes rated for the voltages and common-mode conditions involved. Do not attach an ordinary grounded oscilloscope lead to an arbitrary floating high-voltage node, or remove protective earth to make the measurement.
What Should an RFQ Specify for a Digital Isolator?
Start with the function and operating conditions, then narrow the part list. If a design is already qualified, the complete approved orderable part number should lead the RFQ.
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Define the isolation boundary.
Record the two domains, normal and transient barrier-voltage conditions, and the equipment context for insulation review.
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Map the interface and signal directions.
Include clocks, return data, enables, interrupts and chip selects. State whether the requirement is logic isolation, bus isolation, an isolated transceiver or a gate driver.
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Specify both power domains.
List the supply ranges, input thresholds and output requirements. State whether isolated power conversion is needed and the remote load it must supply.
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Set timing and disturbance requirements.
Use maximum delays, relevant skew, minimum pulse width and receiver setup constraints. Include required CMTI with operating and test conditions.
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Define startup and abnormal states.
Document required defaults, enable polarity, supply sequencing and how the downstream circuit behaves when either side loses power.
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Control the approved variant and evidence.
Confirm package, temperature grade, insulation documentation, quantity and delivery needs. Require proposed alternatives to identify differences explicitly and obtain engineering approval.
For a sourcing enquiry, keep the approved part number, acceptable alternatives and nonnegotiable requirements together. Ask what traceability and inspection evidence will accompany the shipment, and separately confirm who approves the technical substitution. Review YURUNOX's quality-assurance process and purchasing workflow when planning the evidence you need.
Need to source a specified digital isolator?
Send your full part number, quantity and required delivery date. For an alternative-part enquiry, include the interface, channel directions, supply ranges, timing, default state and insulation requirements.
YURUNOX is a component sourcing partner. Final circuit suitability and safety-related substitution approval remain with your engineering and compliance team.
Which Documents Support These Digital-Isolator Decisions?
Manufacturer documentation supports the mechanisms and device examples below. Numerical teaching examples and sourcing scenarios are explicitly illustrative; no physical high-voltage, timing, CMTI or customer-system tests are claimed.
- Texas Instruments — Digital Isolator Design Guide. Two-domain architecture, interfaces and PCB considerations.
- Analog Devices — Anatomy of a Digital Isolator. Coupling and encoding principles; historical technology rankings are not generalized here.
- TI — ISO774x datasheet. Capacitive OOK, channel directions and variant-dependent defaults.
- Analog Devices — ADuM1100 datasheet. Pulse-transformer operation and static-state refresh.
- TI — ISOW774x datasheet. Integrated isolated power conversion and operating conditions.
- TI — High-voltage reinforced isolation: Definitions and test methodologies. Insulation categories and voltage-stress definitions.
- TI — Common-mode transient immunity for isolated gate drivers. Rapid common-mode voltage changes and immunity.
- Analog Devices — AN-1478: Isolated SPI Bus for Distinct System Requirements. SPI round-trip timing and alternate architectures.
- TI — ISO164x datasheet. Bidirectional I²C and clock-direction differences.
- TI — ISO1042 datasheet and UCC21520 datasheet. Isolated transceiver and isolated gate-driver examples.
- TI — How to Meet CISPR 32 Radiated Emissions Limits With ISOW7741. Published layout and emissions example.
- TI — Improve Your System Performance by Replacing Optocouplers with Digital Isolators. Input-drive differences and aging considerations; comparisons must be device specific.