What Is CMOS? How CMOS Chips Work

CMOS stands for complementary metal-oxide-semiconductor. It is a technology that uses p-channel and n-channel MOS transistors together to build circuits, including the logic inside many electronic chips.

Its key idea is simple: one transistor network pulls an output up, while another pulls it down. That helps static digital logic use little power when it is not switching—but does not make every CMOS chip interchangeable.

Exposed integrated-circuit die with fine bond wires connecting it to the package
A chip has circuitry on a die and connections to its package. CMOS describes the technology—not the package shape or a function you can identify from this photograph. Photo: Misterrf, Wikimedia Commons, CC BY-SA 4.0. Uncropped.

What does CMOS mean?

A CMOS logic gate combines two types of transistor so that, in an ideal settled state, one side of the circuit is off. This avoids a continuously conducting path from the positive supply to ground.

The same broad technology can support very different products: a tiny inverter, a microcontroller, an analog circuit or a camera sensor. To choose a part, you still need its function and its datasheet.

Complementary means two transistor types. PMOS and NMOS take different roles in the circuit.

Low static power is not zero power. Switching, leakage and output loads still consume energy.

CMOS does not specify a voltage. Supply range and input thresholds depend on the exact device.

A CMOS sensor and “CMOS battery” are different topics. One is an imaging device; the other is a PC backup-power term.

How are silicon, a MOSFET, CMOS and a chip package different?

Silicon is a semiconductor material. A MOSFET is a transistor whose insulated gate controls a conducting channel through an electric field. CMOS describes a complementary technology using p-channel and n-channel devices. A package, such as QFN or BGA, provides the chip’s physical connections and protection.

Think of a MOSFET as a voltage-controlled switch when learning digital logic. Just remember that real transistors have resistance, capacitance and leakage. They are not perfect mechanical switches, and the historical “metal-oxide-semiconductor” name is not a complete material list for every modern process. Analog Devices’ CMOS glossary gives the basic technology definition.

How does a CMOS inverter turn 0 into 1?

An inverter is a NOT gate: its output is the opposite of its input. The simplest static CMOS version places a PMOS transistor above the output and an NMOS transistor below it. Both gates receive the same input.

The PMOS connects toward the positive supply, labeled VDD. The NMOS connects toward ground. Their joined output is pulled high or low depending on which transistor conducts.

CMOS inverter schematic: a PMOS above an NMOS, with common input gates and a shared output between supply and ground
The basic two-transistor inverter. Diagram: Abaddon1337, Wikimedia Commons, CC BY-SA 3.0. Unmodified.

Which transistor conducts in each state?

Use the schematic and the two settled states below. This is an ideal, unloaded model—not a simulation of switching time or the complete internal circuit of a commercial IC.

  • Input LOW: PMOS is on and pulls the output toward VDD; NMOS is off.
  • Input HIGH: NMOS is on and pulls the output toward ground; PMOS is off.

Swipe the table sideways to see all columns.

Ideal CMOS inverter, after the output settles
InputPMOSNMOSOutput
LOW, near groundONOFFHIGH, near VDD
HIGH, near VDDOFFONLOW, near ground

How to read it: LOW and HIGH are input voltage ranges, not always exactly 0 V and the supply voltage. Real output voltages also depend on load current. Use the IC’s guaranteed limits when connecting two devices.

During a transition, the output capacitance must charge or discharge. Both transistors can also conduct briefly. That is why the low-power explanation applies to the settled ideal state—not to every instant. Toshiba’s CMOS operating-principle lesson illustrates this distinction.

Is a transistor threshold the same as a logic threshold?

A MOSFET’s threshold voltage describes its channel behavior. An IC’s VIH and VIL limits describe guaranteed input recognition. A voltage between the specified LOW and HIGH regions is not a valid third logic state; the receiver’s response is not guaranteed there. Do not assume the boundary is always half the supply.

How do CMOS switches become a working chip?

A two-input static CMOS NAND gate extends the idea. Two NMOS devices in series create a path to ground only when both inputs are HIGH. Two PMOS devices in parallel provide the pull-up path when either input is LOW. The result is HIGH except when both inputs are HIGH.

  1. TRANSISTOR NETWORKSMake logic decisionsNOT, NAND and other gates produce outputs from input states.
  2. CONNECTED GATESBuild functional blocksCombinational and sequential circuits perform arithmetic, store state and control timing.
  3. INTEGRATED BLOCKSPerform a chip’s functionProcessors, controllers and other ICs combine many blocks with interfaces and supporting circuits.

This is a useful learning path, not a claim that every CMOS chip is just a row of identical inverters. Analog amplifiers can need continuous bias current. Memories and mixed-signal circuits have their own architectures. Nor does every transistor have to appear in a simple one-to-one PMOS/NMOS pair.

Why does CMOS still consume power?

Separate the power budget into three questions: what happens at rest, what switches inside the IC, and what the output has to drive. A single “CMOS” label answers none of those quantitatively.

What draws power while the logic is not switching?

Real CMOS devices have leakage and may have always-on internal circuitry. A first estimate for a specified idle condition is supply voltage multiplied by supply current. Read the conditions: temperature, voltage, input levels, operating mode and output load can all matter. A typical room-temperature value is not a worst-case guarantee.

How do voltage, load and switching rate affect power?

For one output swinging from ground to VDD and back, the external capacitive-load term is approximately:

Pload = CL × VDD2 × f

Here, CL is the external load capacitance and f is the number of complete output charge–discharge cycles per second. It is not the count of both edges. If the output does not toggle on every clock cycle, use its actual switching activity.

Illustrative calculation / not a measured chip result

What changes when a 10 pF load moves from 3.3 V to 1.8 V?

Assume the same 1 MHz output-cycle rate and full voltage swing in both cases. At 3.3 V, the load term is 108.9 µW. At 1.8 V, it is 32.4 µW—about 70% lower.

Same 10 pF load and 1 MHz cycle rate; external load term only
3.3 V108.9 µW
1.8 V32.4 µW

What this does not prove: that the whole chip saves 70%, or that you may lower its supply to 1.8 V. The device must support that voltage, and the interface and timing must still work.

Internal switching power and short-circuit current add to this load term. For logic-device estimates, TI’s CMOS power-consumption application report distinguishes internal power-dissipation capacitance from external load capacitance. Do not count the same contribution twice.

How do HC04 and HCT04 differ in CMOS and TTL interfaces?

Traditional TTL logic uses bipolar transistors; CMOS uses complementary MOS devices. But a CMOS part can have TTL-compatible input thresholds. The HCT family is an important example: TTL-compatible inputs do not make the chip a TTL device.

Compare two TI hex inverters. Both contain six independent NOT gates, yet their recommended supply ranges and input limits differ.

Swipe the table sideways to compare both parts.

Selected guaranteed input limits from the TI datasheets
ParameterSN74HC04SN74HCT04
Logic functionSix independent invertersSix independent inverters
Recommended VCC2 V to 6 V4.5 V to 5.5 V
Minimum HIGH input, VIH3.15 V at VCC = 4.5 V2.0 V at VCC = 4.5–5.5 V
Maximum LOW input, VIL1.35 V at VCC = 4.5 V0.8 V at VCC = 4.5–5.5 V

How to use this table: compare a driver’s guaranteed output voltages with the receiver’s guaranteed input limits at the actual supply, load and temperature. These selected input values are not a full substitution approval. Sources: SN74HC04 datasheet, Rev. H and SN74HCT04 datasheet, Rev. F.

Illustrative interface review / based on published receiver limits

A “3.3 V” controller whose guaranteed HIGH is 3.0 V

Assume the controller guarantees VOH ≥ 3.0 V under the intended output load and temperature. The inverter supply is 4.5 V. Now compare the HIGH-level margin:

  • HC04: 3.0 V − 3.15 V = −0.15 V. The input is not guaranteed to register HIGH.
  • HCT04: 3.0 V − 2.0 V = +1.0 V. The HIGH-level requirement is met under these assumptions.

The second result clears one check, not the complete interface. Verify the LOW level, timing, input-current effects and power sequencing too. A 5 V-side output must not feed a 3.3 V input unless that input is explicitly rated to accept it.

One more HCT detail: a valid HIGH below the supply rail can increase supply current. TI specifies additional supply current for off-rail input conditions. Passing the logic threshold does not by itself establish a low-power interface.

For a purchasing team, the decision is straightforward: the same function and a similar part number are not enough. Ask engineering to approve the full alternative before the order is placed. YURUNOX’s purchasing process is a starting point for discussing the exact requirement.

What causes common CMOS circuit failures?

What happens when an input floats or changes too slowly?

An unconnected CMOS input is not a dependable LOW. Noise and leakage can leave it in an uncertain region. A slow transition can also keep the input circuitry between valid states for too long, increasing current and, in some circumstances, causing oscillation.

For unused inputs, follow the device’s termination instructions. Do not confuse an input with an output and tie outputs to a supply rail. Where an input changes slowly, a suitable Schmitt-trigger device may help—but its permitted input conditions still need checking. Adding a capacitor without checking rise and fall times can worsen the problem.

These are documented device behaviors, not a claimed YURUNOX test result. See TI’s report on slow or floating CMOS inputs.

Why can a longer connection change circuit behavior?

A receiver input, PCB trace, cable and oscilloscope probe all contribute to the output load. More capacitance can slow edges and increase switching power. Excessive output current can pull a HIGH below its expected level or raise a LOW.

A useful troubleshooting order: inspect the waveform at the receiving pin with an appropriate probe, check its valid-level margins and edge rates, then compare the actual load with the datasheet test conditions. A logic analyzer can show a decoded 1 while hiding poor analog margin. Follow the manufacturer’s decoupling and layout guidance as well.

What if an input is driven while the IC is powered off?

During startup, shutdown or hot plugging, one device can drive another whose supply is absent. Protection structures may then conduct and back-power the unpowered circuit. Look for an explicit powered-off protection, Ioff or fail-safe input specification; do not assume all CMOS inputs provide it.

Use recommended operating conditions for normal design. Absolute maximum ratings describe stress limits, not a safe continuous operating target. Apply the specified ESD-handling precautions during storage, inspection and assembly.

Does CMOS mean the same thing in cameras and PCs?

What is a CMOS image sensor?

Exposed CMOS image sensor on the circuit board of a Logitech C210 webcam
A CMOS image sensor from a Logitech C210 webcam—not a general-purpose logic gate. Photo: Foreade; Commons edit: Kreuzschnabel. Wikimedia Commons, CC BY-SA 4.0. No further edits.

A CMOS image sensor uses light-sensitive pixels and associated circuitry to turn an optical image into electrical signals. Photodiodes collect charge from incident light; circuitry converts and reads that signal.

Canon’s explanation of CMOS sensors shows why pixel-level conversion and readout matter. The word CMOS describes the technology, while “image sensor” tells you the function.

For selection, look beyond megapixels. Pixel size, shutter type, noise, dynamic range, frame rate and interface must match the application. A moving conveyor can make shutter behavior especially important. CMOS alone does not guarantee a global shutter, freedom from motion artifacts or better performance than every CCD sensor.

Is CMOS the same as BIOS—or the CMOS battery?

No. CMOS is a semiconductor technology. BIOS or UEFI is system firmware. The familiar “CMOS battery” refers to backup power for functions such as the real-time clock and certain settings, depending on the board design. It is not a battery that powers all CMOS chips in the computer.

ASUS motherboard showing a coin-cell backup battery beside a separate BIOS flash-memory chip
A backup battery and BIOS flash chip are separate parts. This example is an ASUS board, not the Dell systems described here. Photo: SamuelPeixoto, Wikimedia Commons. Public domain.
Documented hardware example

Dell separates firmware storage from backed-up configuration

For the Precision 5820, 7820 and 7920 workstations, Dell’s reference guide lists BIOS boot code in 32 MB flash memory and a separate 256-byte battery-backed configuration area in the platform controller hub.

The practical lesson is the separation: losing backup power is not the same as erasing the firmware flash. See Dell’s model-specific memory reference.

Do not turn that example into a universal reset procedure. Settings storage and battery-removal effects vary. Use the service manual for the exact computer or motherboard before attempting a reset.

How do you select a CMOS IC or replacement?

Start with what the circuit must do, then work outward to the electrical interface and the physical orderable part. A broad technology label is useful for understanding, but too vague for an RFQ or an approved alternative.

Swipe the table sideways to review every approval gate.

Condition, evidence and stop boundary for a CMOS part review
Decision checkEvidence to compareStop or escalate when
Function and exact identityFull manufacturer part number, logic function, polarity, channel count and special featuresThe function differs, or a suffix changes the orderable configuration.
Supply and signal compatibilityRecommended supply range, VIH/VIL, guaranteed VOH/VOL, input tolerance and powered-off behavior in both directionsAny guaranteed logic margin is negative, a voltage limit is exceeded or power-sequencing behavior is unspecified.
Timing and actual loadPropagation delay, rise/fall requirements, output drive and capacitive load at the intended voltage and temperatureThe real load or operating condition falls outside the guaranteed test conditions.
PowerQuiescent current, switching activity, external load and any added current from off-rail inputsThe estimate relies only on a typical value or omits a significant operating mode.
Package and environmentPinout, footprint, dimensions, temperature grade and handling requirementsThe footprint, pin assignment, temperature grade or assembly controls do not match.
Sourcing and approvalLifecycle status, packing format, traceability, inspection criteria and engineering sign-offTraceability is incomplete or the alternative lacks documented engineering approval.

Keep the electrical review and the sourcing review connected. A technically suitable part still needs agreed documentation and handling; a traceable part can still be electrically wrong for the board. See YURUNOX’s quality-assurance approach and shipment information when preparing those requirements.

Need to source a specific CMOS component?

Send the full manufacturer part number, required quantity, package and delivery target. If you are considering an alternative, include the supply voltage, interface requirements and engineering approval criteria.

YURUNOX is an electronic-component sourcing partner. Start with the exact requirement so sourcing and technical review can stay aligned.

Where do the technical limits in this guide come from?

The numerical part comparison comes from manufacturer datasheets. The voltage-margin and load-power examples are illustrative calculations, not test reports or customer case histories.

  1. Analog Devices — CMOS glossaryTechnology definition.
  2. Toshiba — CMOS operating principleComplementary inverter behavior and current during transitions.
  3. Texas Instruments — CMOS Power Consumption and Cpd CalculationSCAA035B; internal and load-related switching-power estimates.
  4. Texas Instruments — SN74HC04 datasheet and SN74HCT04 datasheetRecommended supply ranges, input limits and device-specific electrical conditions.
  5. Texas Instruments — Implications of Slow or Floating CMOS InputsSCBA004, revised July 2021; input-transition and floating-input behavior.
  6. Canon Science Lab — CMOS sensorsLight conversion and image-sensor readout.
  7. Dell — Precision 5820 / 7820 / 7920 memory referenceModel-specific separation of BIOS flash and battery-backed configuration storage.

Image sources, authors and licenses appear with each figure. The external images are illustrative and are not presented as YURUNOX facilities, inventory or test evidence.

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